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    by Published on 07-15-2018 05:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. Events,
    4. Semiconductor Advisors
    -semicon-2018.jpg

    We attended Semicon West Monday and Tuesday, the annual show for the semi equipment industry. Its very clear from discussions with all our sources in the industry that confirm that Samsung has put the brakes on spending on memory and that message was reinforced by declines in their expected profitability due to weaker memory pricing. We maintain that a near ...
    by Published on 07-13-2018 05:00 AM
    1. Categories:
    2. Wally Rhines
    Article: Is the RTL Design Flow Broken?-texas-instruments-sr-52.jpg

    This is the fifth in the series of "20 Questions with Wally Rhines"

    From the earliest days of my childhood, I was always trying to find ways to make money – paper routes, lawn mowing, coke sales at football games – I did it all. And, except for a motorcycle ...
    by Published on 07-12-2018 10:00 AM
    1. Categories:
    2. FPGA,
    3. Mobile,
    4. IoT Internet of Things,
    5. Automotive,
    6. Achronix
    Article: Battling SoCs: QCOM vs NVDA vs Samsung-speedecore-efpga.jpg

    If you think the transition to 5G will be anything like the transitions before it to 3G or 4G, you are in for a big surprise. Not only will the transition take longer than either of the previous transitions, its ...
    by Published on 07-12-2018 05:00 AM
    1. Categories:
    2. Artificial Intelligence
    Article: Cadence, Synopsys, and Mentor on FinFETs-deep-learning-jul-2018-min.jpeg

    Deep learning (DL) has become the oracle of our age – the universal technology we turn to for answers to almost any hard problem. This is not surprising; its strength in image and speech recognition, language processing and multiple other domains amaze and shock us, to the point that we’re now debating AI singularities. ...
    by Published on 07-11-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. Events
    Article: Fixing Double-patterning Errors at 20nm-dac-2018-jan-25-cadence-2.jpg

    I attended on Monday, June 25, DAC’s Opening Day, a Cadence-sponsored Lunch panel. Ann Steffora Mutschler (Semiconductor Engineering) was the Moderator and the Panelists were Jim Hogan (Vista Ventures), David Lacey (HP Enterprise), Shigeo Oshima (Toshiba Memory Corp), Paul Cunningham (Cadence).
    ...
    by Published on 07-11-2018 05:00 AM
    1. Categories:
    2. Semiconductor Services,
    3. Events,
    4. EDA Careers
    Article: Cadence, Synopsys, and Mentor on FinFETs-mark-gilbert.jpg

    Welcome to my newly relocated column, I am so excited about my new relationship with Daniel Nenni, and the other esteemed bloggers on SemiWiki. For those who do not know me, I have been a featured columnist on another EDA portal for the past 12-plus years, and in EDA for 20-plus years. ...
    by Published on 07-10-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Events,
    4. Intento Design
    Want to learn 20 nm layout techniques!-id-xplore-min.jpg

    My IC design career started out with circuit design of DRAMS, so I got to quickly learn all about transistor-level design at the number one IDM in the world, Intel at the time. In the early days, circa 1978 we circuit designers actually had few EDA tools, mostly a SPICE circuit simulator followed by manual extraction, manual netlisting, manual layout, manual DRC, and of course, manual transistor sizing. In 2018 the scene has changed for the ...
    by Published on 07-10-2018 05:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Semiconductor Services,
    4. Security,
    5. Intrinsix
    Article: Cadence, Synopsys, and Mentor on FinFETs-mirai-impact-min.jpeg

    You’re excited about the business potential for your cool new baby monitor, geo-fenced kid’s watch, home security system or whatever breakthrough app you want to build. You want to focus on the capabilities of the system, connecting it to the cloud and your ...
    by Published on 07-09-2018 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Mentor Graphics,
    4. Events
    Article: Cadence, Synopsys, and Mentor on FinFETs-caption1.jpg

    Getting your tape-out done on time is hard, but can it be made easier? That was the main topic of Mentor’s Calibre Panel held at DAC 2018, attended by a few key players in IC design ecosystem: Bob Stear, VP of Marketing at Samsung represented the foundry side; from the IP side, Prasad Subramaniam, VP of eSilicon for R&D and Technology; and the fabless side, Satish Dinavahi, ...
    by Published on 07-09-2018 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Fractal Technologies,
    4. Events
    Article: Oasys RealTime Explorer-ip-quality-not-your-problem.jpg

    This year I signed books in the Fractal booth (compliments of Fractal) and let me tell you it was quite an experience. IP quality is a very touchy subject and the source of many more tape-out delays than I had imagined. As it turns out, commercial IP is the biggest offender which ...

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