John Pierce, Product Marketing Director
This webinar runs 41 minutes and here's what I learned:
Analog/RF Design Challenges
My favorite example is the migration to SmartPhones that now support many radios: GSM, GPRS/EDGE, UMTS/HSDBA , WLAN, GPS, Bluetooth. Last year as a late adopter I bought my first SmartPhone from Samsung, the popular Galaxy and quickly learned how limited the battery charge lasted. I'm pleased that this year I've upgraded to the Samsung inFuse and seen my batter life improve from just one day to two days between charges, even when the screen size went from 4.0" up to 4.5".
ADC Design Trends
Chip designers have tighter specs when choosing or designing analog IP, parasitics impact performance more than previous nodes, and this all leads to larger circuits that take much more simulation time for both design and verification.
- foundry qualified/supported models for SPICE
- cell and memory characterization (from Altos)
- SPICE with digital, SI, PCB, RFIC and EM/IR
Make convergence and accuracy the top goals. Accept languages like: Verilog A, SpectreMDL. Support RF analysis and simulate with millions of extracted RC elements.
The Accelerated Parallel Simulator can be used to reduce simulation runtimes by adding more cores in a linear fashion:
Multiple machines in a cluster are supported with: LSF, rsh, ssh, SUN GRID, Loadleveler:
Even RF simulation completes faster in APS for Shooting Newton and Envelope Analysis:
MMSIM 10.1 Release
APS got faster, RF advanced analysis added, reliability analysis added, distributed processing for faster simulation times.
UltraSim with hierarchy simulation handles an EMIR flow.
Demo by Rich Davis
Transient analysis simulation started in Analog Design Environment (ADE) using Spectre:
Same netlist was then rerun using APS on a single core, elapsed time of 6.1 seconds compared to Spectre taking 88 seconds, no loss of accuracy.
Spectre and APS waveform results compared
Use multi-threading and distributed simulation only on larger circuits.
User can trade-off between accuracy and run times, here's what happened when accuracy was loosened up the run time reduced from 6.1 to 4 seconds:
Faster but less accurate results in APS, you decide
The second APS demo circuit was bigger with 1.45 million nodes and 3+ million BSIM devices, APS, multi-threaded with 8 cores, 24K time points, ran in 4 hrs 2 minutes 52 seconds.
The third demo circuit showed Transistor-level Envelope which simulated in 52 minutes, then Fast Envelope was simulated in under 20 seconds using pre-characterized behavioral models:
Error Vector Magnitude plotting was shown on an output node in just a few seconds:
Harmonic balance simulation results were demonstrated next on an amplifier circuit as Loadpull results where input magnitude and phase were varied across a large range in about 1 minute of time:
The final simulation showed HB noise results on a large inductor values:
It looks like Cadence has followed the parallel approach started by Magma's FineSim SPICE and FineSim Pro. Magma doesn't have their own HDL simulator, so Cadence's approach is better if you have to simulate SPICE netlists with VHDL, VHDL-AMS, Verilog-A, Verilog-AMS or Verilog.
Cadence offers UltraSim which handles hierarchy, so they're ahead of Mentor in that regard because ADiT and Eldo are flat simulators.
Synopsys has hierarchical and parallel SPICE simulation, so they go head-to-head with Cadence in this same product area.
You still have to evaluated each circuit simulation vendor on your own designs to determine if it's best for you:
- Netlist compatibility
- Learning curve