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  • Chiplets fuel move to beyond SOCs

    The use of hierarchy in logical and physical electronic design has been one of the most significant developments of our era. It has been accompanied by design reuse at every level from logic gates to complex IP blocks. The two concepts together have enabled the impressive breakthrough designs we see today that include automobile driver assistance, networking, communications and more. For decades, the trend has been to combine functional units to create ever larger SOCs. Monolithic integration has made sense throughout this period.

    This approach, however, has some downsides. Effective implementation of IP reuse means that in moving from generation to generation of SOCs, an increasing amount of the content was being reused. Innovation took place in some parts of the monolithic IC, but many parts remained the same between generations. Yet, at every new node or in every new version the unchanged reused blocks need to be reimplemented so they could be included on the die.

    Another downside of monolithic integration is the necessity to port process-specific blocks, like IOs or memories, each time the core needs to be moved to a new node. These are often complex analog blocks that have many process-specific dependencies that make reimplementation in new nodes difficult. Yield is also an important factor for larger SOCs. As chip size increases the likelihood and cost of a yield defect increase too. If you think about it, building large monolithic SOCs goes against the some of the ideas behind enabling reuse and employing hierarchy.

    Design approaches come in and out of fashion depending on the prevailing technical and economic pressures. A new approach known as chiplets appears to be coming of age to enable higher performance and lower cost designs. The roots of this approach were established decades ago in multi-chip modules (MCMs). Initially MCMs were implemented using ad-hoc parallel connections between separate die placed together in a single package. Today a number of trends are making this approach attractive again.

    Article: Intel's x86 - Foundry Breakup Comes into View-chiplet-image.jpg

    A white paper entitled “Chiplets - Taking SoC Design Where no Monolithic IC has Gone Before” by Achronix discusses the renewed appeal of this approach and talks about several different ways chiplets can be used. Unlike MCM’s with older generation parallel interfaces, there are now a variety of high speed and efficient serial protocols that can be used to facilitate chiplets. However, the white paper points out that more standardization is still needed. Chiplets often do not need heavy weight protocols that are used for off chip communication, though things like Ethernet and PCIe can work well in some instances.

    Chiplets really shine when specialized blocks like SerDes, NIC, memories and RF circuitry can be built with their own optimal process node. A side benefit is that they can be used to reduce noise that often occurs in monolithic chips between analog and digital blocks. In one package there could be a combination of nanometer FinFET, GaAs, Flash and even FPGA, each on their own substrate.

    Achronix has a new offering called Speedchip that takes their popular Speedcore embeddable FPGA fabric and moves it into chiplets. High speed customizable FPGAs that are interfaced to other larger blocks can be used in a number of novel new ways. In their white paper Achronix outlines several scenarios where an FPGA chiplet can handle tasks such as flow-through compression or cryptography under the control of a CPU running at a much lower clock rate. This boosts performance and saves power.

    Chiplets are a promising approach that have a lot to offer. There are huge advantages in only having to update the parts of a design that need it when a new product generation is created. The Achronix white paper does a good job of covering the motivations for using chiplets and their advantages. It also talks about the design considerations around their use. They also discuss how chiplets are connected together today and what directions this might take in the future. The full white paper can be downloaded from the Achronix website. I always find it interesting when old ideas are updated and applied to solve new problems – this is an excellent example of that trend.