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  • SPIE Advanced Lithography Conference 2019 Overall Impressions

    Last week I attended the 2019 SPIE Advanced Lithography Conference. I gave two presentations, attended dozens of papers and conducted three interviews. I will be doing some detailed write ups particularly on EUV but I am waiting for the presentations from several of the papers. In the mean time I thought I would put some overall impressions together.

    Article: TSMC ♥ Cadence-spie-advanced-lithography-conference-2019.jpg

    Canon event

    The conference began for me on Sunday morning at a Canon private briefing for about 50 customers and partners where I was an invited speaker. One of the other speakers was Yan Borodovksy, a former senior fellow at Intel (Intel’s highest technical level), now retired and a fellow of SPIE. Yan made what I thought was the funniest comment of the entire week. He basically said, “Moore’s law isn’t dead, it just had a stroke and stopped moving on one side”.

    Nikon LithoVision
    Where the Canon event was private and limited to customers and partners, Nikon’s LithoVision is a more public event attended by over 500 people. I was also invited to speak at LithoVision and I have written my talk up here.

    My favorite talk of the event was Anton Devillier’s animated and entertaining talk about what he would tell lithographers if he could go back in time. He had a very cool illustration of a worm hole and talked with so much energy that at one point his lavalier mic went flying.

    Overall Conference
    I thought the overall conference was relatively quiet this year. Last year was as Chris Mack put it, “The year of Stochastics” where it seems everyone had just woken up to the idea that we had to actually make EUV work and now had to face the practical problems. This year to me was much more a year of quiet progress and continuing investigation.

    My impression was ASML and Imec were the key presenters this year providing a lot of the material. Imec alone was first author on 32 papers and coauthors on even more

    There was a lot of papers on EUV against the background that after many years waiting for implementation, that EUV is actually ramping up in production now.

    The following isn’t specific to the conference but sets a background on EUV.

    Samsung is currently ramping up a 7nm EUV based foundry logic process with approximately 7 EUV layers including what we believe to be a 36nm metal pitch printed with EUV. TSMC has been in production with their optical 7nm 7FF foundry logic process since last year and is now ramping their 7nm 7FF+ process with 5 EUV layers. We believe the minimum EUV pitch on 7FF+ is 40nm. The word out of TSMC is that the process is going very well including the performance of EUV. Later this year TSMC is expected to begin risk starts on a 5nm foundry logic process with more extensive EUV usage. We believe the 5nm process will include 28nm minimum metal pitches produced by EUV. Once again, the word out of TSMC is this process is going very well including EUV. Intel is also working on EUV for their 7nm process due in 2020. EUV is clearly ramping into high volume manufacturing and by all accounts the implementation is going well.

    ASML provided updates on the current 0.33 NA systems and the 0.50 NA (high NA) system in development and I sat down and interviewed Mike Lercel (Director of Strategic Marketing) as well. I will provide a more detailed write up on these systems once I get the ASML presentations. A few initial observations:

    1. There are now 40 EUV systems in the field representing proximately $4 billion dollars of investment by device manufacturers.
    2. ASML is expected to ship 30 EUV systems this year (some Q1 shipments may already be in the 40-system number) and 40 more EUV systems next year. That represents approximately $3B and $4B of additional investment for 2019 and 2020 respectively.
    3. ASML will begin shipping the NXE3400C system later this year with improved uptime and throughput.
    4. The High NA system design is well underway and ASML and Zeiss (the lens manufacturer) are expending their facilities in preparation for production.

    Imec presented work in multiple different areas and I also had the opportunity to interview Greg McIntyre (Director of Advanced Patterning), John Peterson (Principle Scientist) and Yasser Sherazi (R&D Team Leader for Design). I will be doing a detailed write up of the Imec work once I get the presentations from them.

    1. John Peterson gave an interesting talk that showed just how little we understand how EUV photoresist works, Imec along with KMLabs has announced a new lab to study reactions in EUV photoresist in the attosecond to picosecond range (E-18 to E-12 second range).
    2. Imec has identified cliffs in the EUV photoresist process where on the low CD side there is an exponential increase in micro birding or missing contacts and on the high CD side there is an exponential increase in broken lines and merging contacts. New at this year’s conference was characterization of a defect noise floor between the two cliffs. The noise floor was around E-7 in one experiment and then improved to around E-8 with a different photoresist and complex filtration. I asked John Peterson whether these limits were fundamental. He said that for an 80mJ/cm2 dose the photo shott noise limits was approximately E-11 so we are no where near the limit yet.
    3. Imec also present work on sequential infiltration synthesis (SIS) that provides smoothing and improved etch resistance of EUV photoresists.
    4. There were several Imec papers on design improvements. Buried power rails and backside power distribution are powerful scaling boosters. Device architectures such as CFETs can drive cell heights all the way down to 3 tracks.

    EUV uses complex multi layers reflective masks, the absorber pattern on the mask surface has a thickness that can lead to 3D shadowing effects at small feature sizes and or larger incident radiation angles such as what we will see with high NA EUV systems. Veeco make deposition and ethc tools used to make EUV masks and they are involved in work to change to high-k absorber materials enabling thinner absorber films. I interviewed Meng Lee (director of product marketing) about etching of hig-k materials.

    In summary, there was a lot of interesting up-dates on EUV systems and processing as well as new design technique to enable future scaling. I will be writing this up in detail over the next couple of weeks so keep your eye on SemiWiki for my articles.

    Also read: LithoVision 2019 - Semiconductor Technology Trends and their impact on Lithography