You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • Low Power SRAM Complier and Characterization Enable IoT Applications

    If you are designing an SOC for an IoT application and looking to minimize power consumption, there are a lot of choices. However, more often than not, looking at reducing SRAM power is a good place to start. SRAMs can consume up to 70% of an ICís power. SureCore, a leading memory IP supplier, offers highly optimized SRAM instances for such applications. They took the approach of looking at first principles to effectively rethink how to reduce SRAM power. Making good use of their approach, they have developed memory compilers that deliver front and back end views of the memory instances required by their users. As part of this, accurate timing and power views are needed to complete designs incorporating these instances.

    Designers utilizing SRAM instances look to Liberty model files to provide characterized timing and power information so that system level simulations are fully accurate. Generating this characterization data is computationally intensive according to sureCore. However, they make use of advanced tools and techniques to make the task manageable. In my conversations with them they discussed how they manage the characterization process for their EverOn 40ULP family of SRAM instances.

    Article: Going to DAC 2013 in Austin? The Country's Best Barbecue is a 20 Minute Walk-surecore-characterization-flow.jpg
    For each synchronous input, for a range of clock and data edge speeds, typically around 7 of each, they would need to examine 49 (7x7) setup and hold values. On the power side, they need to look at static and dynamic power for operation modes such as read and write, as well as the full range of power down and sleep modes that are available. As you can see this becomes an exponentially growing problem as different PVTs are added and consideration is given for each of the different configurations available.

    The EverOn family consists of 276 different SRAM memories, that vary in aspect ratio, word count and word length. The operating range of this family is 0.6V to 1.21V, creating a large PVT space for full characterization. A frontal brute force approach to simulation could easily require 24 hours per instance, which would be unworkable. One aspect of their characterization solution is to take advantage of the most recent and advanced features of Liberate-MX provided by Cadence.

    They explain how several features in Libterate-MX accelerate the process. First Liberate-MX can carefully prune the netlist during timing estimation to only include only the circuit elements necessary to provide an accurate value of the timing parameter being characterized. The other technique they employ is using interpolation to provide power numbers over a wide range of memory configurations. SureCore has used full characterization runs on sample memory sizes to validate the interpolation results and has seen excellent results.

    Article: Going to DAC 2013 in Austin? The Country's Best Barbecue is a 20 Minute Walk-surecore-read-power.jpg
    The Cadence tool suite is used to optimize runtime while maintaining accuracy. Liberate-MX cleverly dispatches leaf level pieces of the memory instance to Spectre XPS for detailed SPICE results. With smaller process nodes there has been an increase in PVT corners, and Monte Carlo analysis is becoming necessary. The number of simulation runs needed has exploded. They use the new Super Sweep technology, leveraging simulation steps that can be shared between different corners, accelerates simulation. SureCore has seen a 2x speed up in runtime and an improvement in accuracy from these techniques.

    However, a substantial part of reducing their computational requirements for memory characterization come from the flow that sureCore has developed, including specific net listing techniques to provide optimal inputs to each step in the flow. They report dramatic reductions in net list sizes for timing, static and dynamic power.

    SureCore also focuses on validation to ensure the characterization flow is producing safe and accurate results. They have a suite of Python scripts that check simulation results to ensure that the models perform properly. They even run checks that validate that the correct internal structures were included in the characterization runs. On top of this they run stressed simulations with Monte Carlo variation.

    SureCore is filling a need for low power SRAM IP, which is absolutely necessary for edge devices in this era of IoT and mobile applications. I found it fascinating to learn about their comprehensive process dedicated to characterization. They have white papers on their website that offer interesting information on their technology. Without a flow like this, anyone would be greatly challenged to deliver high quality and consistent IP deliverables.