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Measuring Up 7nm IP

Measuring Up 7nm IP
by Daniel Nenni on 08-17-2018 at 12:00 pm

The Linley Group is an industry-leading source for independent technology analysis of semiconductors for networking, communications, mobile, and data-center applications. Their Microprocessor Report is widely read as a source of un-biased, no-nonsense analysis of technologies and trends. So, when they dig into something it’s worth reading.

Mike Demler recently did a piece on eSilicon entitled “eSilicon 7nm SerDes Hits 56GBPS – NeuASIC Platform Includes AI Accelerators for 2.5D/3D ICs”. I know Mike, and he’s one of those “just the facts” kind of guys that speaks from experience, absolutely. I have a copy and here is a quick summary with a link to the report:

The report spends some time reviewing eSilicon’s 7nm SerDes IP. This one IP block has become Star IP for many customers. It implements high-speed serial communication between chips and it’s performance is critical to achieving the overall throughput needed for advanced ASICs. The report goes into some detail about eSilicon’s 56G SerDes – its programmability to allow designers to tune power and performance for long or short reach channels for example. Several other performance statistics about eSilicon’s SerDes are also disclosed in the report.

22209-esilicon-serdes-7nm.jpg

eSilicon’s 56G SerDes test chip on the bench

eSilicon’s HBM2 PHY is also discussed. This IP implements the physical channel between an ASIC and HBM2 memory stacks. It’s available for a variety of technologies and foundries. The use of this IP to implement 2.5D designs with integrated HBM2 memory stacks on a silicon interposer is also discussed. eSilicon’s line of content-addressable memories are also reviewed in some detail, including application scenarios and performance comparisons with other vendors. The report also delves into eSilicon’s platform focus for its IP offerings, with specific packages for AI and high-performance networking. The details of what goes into a high-performance networking chip are discussed. The methodology eSilicon uses to create platform-based AI chips is also reviewed in some detail.

The report concludes with a frank assessment of market dynamics for the highly competitive networking and AI markets – where eSilicon fits well, and what challenges they will likely face. I believe companies like eSilicon that both develop IP and use the same IP for their ASIC business have a built-in advantage in terms of proven IP quality. As part of my research, I hear all of the bad IP stories from the top semiconductor companies and the foundries. IP really is critical and silicon-proven IP is quite valuable. This Linley report is definitely worth reading. You can download a free copy from the eSilicon website.

Also read: eSilicon and SiFive partner for Next-Generation SerDes IP

About eSilicon
eSilicon is an independent provider of complex FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete 2.5D/HBM2 and TCAM platforms for FinFET technology at 16/14/7nm as well as SerDes, specialized memory compilers and I/O libraries. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com

About The Linley Group
The Linley Group is the industry’s leading source for independent technology analysis of semiconductors for networking, communications, mobile, and data-center applications. The company provides strategic consulting services, in-depth analytical reports, and conferences focused on advanced technologies for chip and system design. The Linley Group also publishes the weekly Microprocessor Report. For insights on recent industry news, subscribe to the company’s free email: Linley Newsletter. www.linleygroup.com

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