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  • Optimization and Reliability for FinFET designs at #55DAC

    TSMC is the leading foundry worldwide and they make a big splash each year at the DAC exhibit and conference, so I stopped by their theatre area during the presentation from IP vendor Moortec to see what's new this year. Stephen Crosher was the presenter from Moortec and we had exchanged emails before, so this was the first time that we had a chance to meet in person.

    Biggest Challenge of Adoption of 3D IC Technology-moortec-tsmc-dac-min.jpg

    Designing an SoC for use in a system is a complex task these days, and even premier design companies like Apple have reported performance issues with their newest MacBook Pro laptops because as they were warming up under high loading the fans came on to cool the system off and then the CPU frequency was throttled to lower the temperature, but it was throttling back too much and actually performing slower than the previous CPU generation used. Fortunately for Apple they will issue a software fix to correct the clock throttling issue. Modern day SoC projects require that the design team have a plan for an optimized system that is also reliable.

    Biggest Challenge of Adoption of 3D IC Technology-apple_macbook_pro_update_data_manipulation_simulations_07122018-min.jpg
    MacBook Pro overheats, throttles frequency too much. Source: Apple

    Some of the challenges in FinFET design are well known:

    • Higher thermal density
    • IR drop and PDN (Power Delivery Network) issues
    • Noise between coupled signals and injected into the substrate
    • Reaching timing closure


    With each successively smaller process node we enjoy the benefits of increased gate densities, but at the expense of also increased power densities that can cause reliability issues. Narrower and higher-resistance interconnect layers impact timing to a greater degree and increase the variation effects. Add up all of these issues and it makes reaching timing closure even more difficult.

    The Moortec approach to these challenges is to provide monitoring IP placed strategically within certain regions of an SoC, where the PVT sensors communicate to a controller that can then perform actions like scale the voltage, or throttle clock frequencies in order to have a reliable chip. Experts at Moortec have engineered this IP across multiple process nodes:

    • 40nm
    • 28nm
    • 16nm
    • 12nm
    • 7nm


    Some of the benefits of using this pre-built monitoring IP in your next chip include a reduced risk of failing to meet specs, an improved yield at the foundry, better reliability and chip lifespan, and no up-front development costs to design and qualify your own IP. With the Moortec IP embedded you can better implement dynamic or adaptive schemes like DVFS (Dynamic Voltage Frequency Scaling) or AVS (Adaptive Voltage Scaling).

    Many chip segments will benefit from embedded monitoring:



    • Datacenter - thermal management, high gate densities, leakage currents, CPU temperatures
    • Consumer - process variability, thermal management, localized process variability
    • Automotive - reliability and thermal management, real-time monitoring throughout vehicle lifetime
    • IoT - edge devices that sense and monitor, manage multiple supply levels to meet power specs


    Moortec has been an IP Alliance Member with TSMC since 2010, starting at the 40nm process node, and in 2016 they received a partner of the year award from TSMC. At DAC there was news from Moortec about supporting the 40nm ULP CMOS technology, useful for the IoT marketplace. It was fun to meet the Moortec team in SFO and see their customer list continue to grow with tier one clients in diverse industries.

    Biggest Challenge of Adoption of 3D IC Technology-20180625_171832-min.jpg
    Moortec team at DAC in SFO

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    About Moortec
    Established in 2005, Moortec provides compelling embedded subsystem IP solutions for Process, Voltage & Temperature (PVT) monitoring, targeting advanced node CMOS technologies from 40nm down to 7nm. Moortec’s in-chip sensing solutions support the semiconductor design community’s demands for increased device reliability and enhanced performance optimisation, enabling schemes such as DVFS, AVS and power management control systems. Moortec provides excellent support for IP application, integration and device test during production. Moortec’s high-performance analog and mixed-signal IP designs are delivered to ASIC and System on Chip (SoC) technologies within the consumer, mobile, automotive, high performance computing and telecommunications sectors. For more information, please visit www.moortec.com, follow us on Twitter and LinkedIn.