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  • Legato Reliability Solution

    Article: The First 14nm FinFET Wafer Sighting!-caption.jpgThis week Cadence introduced Legato™ Reliability Solution, intended to address increased challenges in designing high-reliability analog and mixed-signal ICs for automotive, industrial, aerospace and defense applications.

    “Since electronics are the key elements in many mission-critical applications, designing the chips to meet requirements across the entire product lifecycle has become a huge challenge,” said Tom Beckley, Cadence senior vice president and general manager, custom IC and PCB Group.

    Based on both the existing Cadence’s Spectre simulation and Virtuoso custom IC design platform, Legato provides analog designers with the needed tools to manage their design’s reliability from initial test through active life and aging phases, a complete product lifecycle coverage.

    “Designers are faced with the challenge of designing across the entire lifecycle, including eliminating the test escapes that become field failures early in the life cycle, preventing thermal overstress from operating in extreme conditions like under the hood of a car, and designing for 15 years or more of operating lifetime.” stated Tom Beckley further.
    Article: The First 14nm FinFET Wafer Sighting!-fig1a.jpg
    To find out more on how Legato addresses reliability challenges, I talked with Product Management Director, Hany Elhak and from his team, Product Manager Arthur Schaldenbrand of Cadence Circuit Simulation and Library Characterization product lines.

    Art provided background on why design for reliability is needed such as stringent zero-defect requirement in automotive applications. IC products are subjected to not only mechanical or electrical stress, but also temperature stress. Mission critical reliability can translate to the difference between life and death as captured in Fig 1a.
    Article: The First 14nm FinFET Wafer Sighting!-fig1b.jpg

    Cadence Legato Reliability Solution integrates capabilities to address the three phases of product lifecycle, which is illustrated in figure1b as the well-known “bathtub curve”, showing failure rates during a product lifetime.



    Early Stage & Analog Defect Analysis

    Traditionally analog ICs product defect-oriented testing is achieved by just performing Article: The First 14nm FinFET Wafer Sighting!-fig2a.jpgfunctional and parametric tests. In this release as captured in figure 2a, Cadence introduces a simulation engine that expands the test methodology to enable both eliminating die with manufacturing defects and resulting test escapes, the main source of early failure in IC designs.

    It can also be used to optimize wafer test, reducing the number of tests required to achieve the target defect coverage by eliminating over-testing and potentially reducing the number of tests up to 30 percent. Customer report showed the analog defect simulation acceleration is up to 100x, reducing test cost.


    Useful Life and Electro-Thermal Analysis
    Article: The First 14nm FinFET Wafer Sighting!-fig2b.jpgKey factor to ensuring a product survival during its useful life stage is through testing and analyzing its use in a realistic operating condition. For example, in automotive applications the actual usage involves significant temperature rise during normal operation due to on-chip losses and power dissipated in the switches. In addition, these components need to operate in hostile environments under the hood of an automobile. The combination of high-power dissipation in a high-temperature environment can result in thermal overstress that can result in failure during normal operation.

    Cadence introduces dynamic electro-thermal simulation engine that allows designers to simulate this on-chip temperature rise and validate the operation of over temperature protection circuits (see figure 2b). This is relevant to prevent both thermal overstress and avoids its related premature failures such as in automotive products.

    Late Stage and Advanced Aging Analysis
    Article: The First 14nm FinFET Wafer Sighting!-fig2c.jpgDuring a product-life’s late stage, it is crucial to assess its integrity while going into a degradation period. Advanced aging analysis enables accurate prediction of product wear-out by analyzing aging acceleration due to temperature and process variation.

    Cadence has existing aging analysis products like RelXpert and AgeMOS to analyze the device degradation due to electrical stress. In this release, Cadence takes a step forward, enhancing aging analysis to include the effects that accelerate device wear-out, including temperature and process variation. A new aging model is also provided for device degradation in advanced nodes with FinFET transistors. As shown in figure 2c, this holistic approach to aging analysis allows designers to achieve their design lifetime targets with less over-design.


    Q: Could you comment if Legato has any tie to the recently Virtuoso release 18.1?

    “It’s version agnostic and it is available for testing now,” said Hany. I prompted him further on feature support for TDDB (as during its technology conference update last week, TSMC stated of having trouble in dealing with stringent N7 TDDB, although were able to overcome it). “Yes, TDDB is taken into account. In fact, we take one step further to consider aging due to temperature and process variation. It is not an isolated scenario as they must be analyzed together.”

    Q: Which process technologies Legato is recommended for or has been qualified in?
    “It has been qualified by several IDMs and includes matured nodes technologies intended for automotive applications. For the aging model, we released a new aging model for device degradation in advanced nodes with FinFET transistors. We are working with customer for further endorsement,” said Hany Elhak. Cadence also received endorsement from Infineon Austria. “Analog defect simulation is becoming very important for us to meet our customers’ expectations,” stated Dieter Härle, a project manager at Infineon Austria. “We tested the Legato Reliability Solution and were able to accelerate the simulation time by a factor of more than 100. We verified the solution and plan to adopt it for use in our production flow.”

    Q: Is Legato considered a sign-off tool or intended for reliability analysis tool (what-if) as part of the development process?
    “It is intended for reliability analysis rather than for sign-off. It offers a comprehensive reliability analysis using both Virtuoso platform and Spectre accelerated parallel simulator to address challenges in designing high-reliability ICs in automotive, medical, etc.” Hany responded.

    For further info on Legato Reliability Solution, please check product datasheet HERE.