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  • Samsung 10nm 8nm and 7nm at VLSIT

    I got a tip sheet today for the upcoming 2018 Symposia on VLSI Technology & Circuits to be held June 19th through 21st in Honolulu, Hawaii. There is some interesting information on Samsung's 10nm, 8nm and 7nm processes in the tip sheet:

    10nm

    At 10nm the Samsung process has a Contacted Poly Pitch (CPP) of 68nm and uses single diffusion breaks (SDB) to minimize standard cell width. Depending on the cell type SDB can provide up to a 25% reduction in the cell width, although in actual designs 20% is more typical.

    The Metal 2 Pitch (M2P) is 48nm. The cell height is 10 times the fin pitch of 42nm = 420nm resulting in 8.75 tracks.

    There are 3 fins for each nFET and pFET respectively.

    The resulting transistor density using a weighting of 60% NAND cells and 40% scanned flip flop cells yields 54.55 million transistors/mm2. This is in comparison to our estimate of 55.10 MTx/mm2 for TSMC.

    8nm
    I found the 8nm information particularly interesting because this is the first time I have seen 8nm values for Samsung.

    The 8nm CPP is 64nm and uses a SDB.

    The M2P is 44nm. The cell height is 9 times the fin pitch of 42nm = 378nm. The track height is 8.59. The minimum metal lines are produced using LE4 (Litho-Etch 4 times). This is more complicated than self-aligned double pattering (SADP) but LE4 allows bidirectional layouts whereas SADP requires unidirectional layouts.

    There are 2 fins for each nFET and pFET respectively. Fin depopulation is common as cell heights shrink. Presumably some optimization of fin height or parasitics has been done to compensate for lost drive current going from 3 fins to 4 fins.

    Figure 1. illustrates the layout of 10nm and 8nm cells.

    CES 2013 Trip Reports (Win an iPad Mini!)-samsung-10nm-8nm.jpg


    Figure 1. Standard cell scaling from 10nm to 8nm.

    The calculated transistor density for 8nm is 64.40 MTx/mm2 providing an 18% improvement over 10nm.

    7nm
    There are several outstanding questions about Samsung's 7nm process around metal pitches and types and hopefully when the full paper is released they will be answered.

    In the tip sheet the fin pitch is listed at 27nm and CPP of 54nm. I have heard 57nm for CPP and I suspect that while 54nm is supported, actual standard cells use 57nm similar to TSMC. AC performance is 20-30% better and power is reduced by 50-60% versus 10nm.

    EUV is used for critical middle-of-line (MOL) and back-end-of-line (BEOL) layers. I am expecting 36nm as a minimum metal pitch, but the tips sheet didn't disclose any metal pitches.

    The SRAM cell size for Samsung is 0.0262um2 the smallest SRAM cell size of competing 7nm/10nm processes from GLOBALFOUNDRIES and TSMC (7nm) or Intel (10nm) processes.

    The calculated transistor density is 101.23 MTx/mm2 based on what we know today although there is some uncertainty in M2P and track height in that calculation that will hopefully be cleared up in the full paper. The calculated density improvement versus 10nm is 1.86.

    101.23 MTx/mm2 is slightly less than our calculated value for Intel's 10nm process and slightly more than our calculated density for GLOBALFOUNDRIES and TSMC's 7nm processes.

    Conclusion
    With a great location and this kind of information being presented it should be a valuable and enjoyable conference.


    Also Read: Samsung is Starting 7nm Production with EUV in June


    About the Symposia
    Professors Shoji Tanaka and Walter Kosonocky, founders of the Symposia, first organized the VLSI Technology Symposium in 1981 with the hope of offering an opportunity for world’s top technologists to engage in an open exchange of ideas on what was quickly becoming a revolution in the world’s industrial capability. Since then, the Symposium has been held annually and has grown to be an important and valuable event for people working in the VLSI business. The presentation of high-quality papers has made it possible for attendees to learn about new directions in the development of VLSI technology. The friendly atmosphere has made this an enjoyable learning experience.

    The Symposium on VLSI Technology has alternated each year between sites in US and Japan. In 1987, the first Symposium on VLSI Circuits was held in conjunction with the Technology Symposium in recognition of the growing interest to provide the same small but intense and open forum for discussing circuit and system implementations. Since then, this annual meeting has increased its value over the past 26 years. We are confident that so many new technologies and circuits were introduced in the past Symposia and thus have contributed to the prosperity of the world. Its sponsors continue to be the IEEE Electron Devices Society and Solid-State Circuits Society, and the Japan Society of Applied Physics in cooperation with the Institute of Electronics, Information and Communication Engineers.

    For many reasons, these meetings have remained linked for the past years to provide opportunities for technology people and circuit and system designers to interact with each other. These interactions are augmented with short courses, invited speakers and several evening rump sessions. In recognition of the efforts of organizers, authors and participants to make the Symposia successful, there is ample banquet and entertainment prearranged.

    The 2017 meeting was held in Kyoto, Japan. This year it will be returning to the Hilton Hawaiian Village in Honolulu, Hawaii in June of 2018.http://vlsisymposium.org/