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  • Converter Circuit Optimization Gets Powerful New Tool

    DC converter circuit efficiency can have a big effect on the battery life of mobile devices. It also can affect power efficiency for wall-power operated circuits. Even before parasitics are factored in, converter circuit designers have a lot of issues to contend with. Optimizing circuit operation is essential for giving consumers what they want. Switching converters are light years ahead of old-school transformer based designs. However, switching converters are often operating at high frequencies that can create challenges for efficient operation. In addition to parasitic inductances and additional current from reverse recovery effect, the PowerMOS devices themselves do not operate as ideal devices.

    It’s necessary to understand that PowerMOS devices are really an assembly of large numbers of parallel intrinsic devices with a complex and distributed structure. As such, switching does not occur simultaneously across all the intrinsic devices. Within a PowerMOS RC delays greatly affect Vgs present at the gates in the low and high side transistors. Previously it has been difficult to run simulations that take this into consideration. Fine grain extraction of gate, source and drain interconnect is not a good application for traditional rule based extractors. Designers have struggled with this lack of visibility up until now.

    Recently Magwel has released a tool specifically targeted at realizing comprehensive and accurate simulation of converter circuits, including the complex internals of PowerMOS devices. Magwel’s PTM-TR does several unique things to provide transparency into the detailed switching behavior of PowerMOS devices. PTM-TR uses a solver based extractor to correctly and accurately determine parasitics for the internal metallization within PowerMOS devices. The gate regions are divided up according to user set parameters and the intrinsic device model is applied to create a simulation view of the device that incorporates full internal structure. This model is known as a Fast3D model and is used by PTM-TR with Cadence Spectre® to co-simulate dynamic gate switching behavior at each time step of circuit operation.

    Want to learn 20 nm layout techniques!-ptm-tr-features.jpg


    Because the Fast3D model is used in conjunction with Spectre circuit simulation, it can be used with test benches, or to perform any desired simulation, such as corner analysis. PTM-TR comes with the additional benefit of showing graphically the internal field view of the device at each time step. This is a direct benefit of the co-simulation. Magwel has a fascinating video on their website that shows how the field view of the PowerMOS device can be useful in understanding dynamic switching performance.

    The Magwel video highlights how Vgs reported in simulation can differ from Vgs at each individual gate location. At one time step in the transition of the half-bridge, the delta in Vgs is ~2V. This can have a large effect on shoot through current. Also, during early switching with only certain sections of the device turned on, higher than expected current densities are possible – leading to EM and thermal issues. With PTM-TR designers can modify and test PowerMOS devices to achieve optimal performance.

    Want to learn 20 nm layout techniques!-ptm-tr-time-step.jpg


    PTM-TR is part of Magwel’s complete family of power transistor modeling tools. The base product, PTM, reports Rdson and static power and current per layer. PTM-ET gives insight into combined electro-thermal performance of PowerMOS devices. PTM-ET uses thermal models that can include heat sources and sinks on the die, as well as thermal properties of the package.

    The PTM-TR video can be viewed on the Magwel website. More information about the PTM product family and Magwel’s solutions for ESD and power distribution network analysis can be found there as well.