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  • A Picture is worth a 1,000 words

    Semiconductor IP re-use is a huge part of the productivity gains in SoC designs, so instead of starting from a clean slate most chip engineers are re-using cells, blocks, modules and even sub-systems from previous designs in order to meet their schedule and stay competitive in the market place. But what happens when you intend to re-use some IP with the notion of adding some new features to it? How in the world do you learn about a previous IP block if you weren't the person responsible for creating it in the first place? If someone hands you 10,000 lines of VHDL or SystemVerilog code, how would you go about learning how it was created in order to modify it? Sure, you could read the documentation, or even start to just look at the source code to glean some insight. Is there a better way? Yes, there is a better way and that better way is to read in your HDL code and then automatically create a graphical representation of it using blocks and state machines.

    Sigasi is an EDA company with a tool that does just that, however at first use of their BlockDiagram view you may just see a bunch of cell instances connected with wires which can be a bit messy to infer much info from:

    New SystemVerilog Assertions book based on 1800-2012-block-diagram-min.jpg

    If you could color instances and use some busses then the block diagram would be more legible and make understanding its operation a whole lot easier:

    New SystemVerilog Assertions book based on 1800-2012-block-diagram-filtered-min.jpg

    The Sigasi Studio tool also automatically finds state machines in your HDL code and creates a StateMachine view, which is how most IC designers think of their logic to start out with:

    New SystemVerilog Assertions book based on 1800-2012-state-machine-min.jpg

    Here's an updated view of the same state machine, this time with some coloring and re-grouping to emphasize state transitions:

    New SystemVerilog Assertions book based on 1800-2012-state-machine-filtered-min.jpg

    So how do you go from the default diagrams created by Sigasi Studio to the ones with colors and groupings?

    You use something called a Graphic Configuration file. Some of the benefits of using a text file for Graphic Configuration are:

    • Easier to manager with your favorite version control system, allowing easy compares and merges.
    • Debug is straight forward, saving you time.
    • Sigasi Studio features like auto-complete, validations and formatting are all built-in to the tool.

    With a Graphic Configuration file you can do five important tasks:
    1. Group states, instances or wires together.
    2. Hide states or blocks.
    3. Collapse blocks.
    4. Coloring, as shown in the two examples above
    5. Regex matching.

    Some Examples
    Let's say that you want to color a specific block to green and have the internals hidden, the Graphic Configuration file syntax is:
    block my_block { color green collapse }

    That was pretty simple and compact to write.

    Continuing that first example a bit, now we want to access a block within a block, calling for a nest configuration like this:

    block my_block {
    color green
    block block_within_name {
    color red

    Changing how your state machine looks is just like the block diagram we just learned except the first keyword is "state" instead of "block".

    A picture really is worth a 1,000 words, and now with the automated visualization feature in Sigasi Studio you can have a lot more control over how it looks by using a Graphic Configuration file, therefore making understanding your HDL code much easier than staring at text alone. To read more about this topic there's a blog article written by Titouan Vervack at the Sigasi site.