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  • Customizable Analog IP No Longer a Pipe Dream

    Configurable analog IP has traditionally been a tough nut to crack. Digital IP, of course, now provides for wide configurability for varying applications. In the same way that analog design has remained less deterministic as compared to digital design, analog IP has also tended to be less flexible. However, the tide may be turning for configurable analog IP. The Brazilian analog IP company Chipus has been working with MunEDA tools to bring this about.

    Of course, it all starts with a robust design where forethought has been given to ensuring a wide operating range. For Chipus this is the basis of their CM4018hlf flexible ring oscillator. This circuit is tunable to frequencies between 200kHz and 20MHz – quite a large range. Chipus was founded in 2009 and now offers over 180 IP blocks, many of them silicon proven and in production. They are using MunEDA’s WiCkeD to design across this wide range of frequencies and then offer models for any desired operating point on their web portal. The alternative of manually tuning and then optimizing the design for a wide range of frequencies would be prohibitive.

    Article: Variation-Aware Design: A Hands-on Field Guide-muneda-oscillator-min.jpg


    To help us better understand the behind the scenes work that was done to enable this wide range of configuration, the folks at Chipus put together a demonstration design using a similar set up. I had a chance to look over their write up on this and found it quite interesting.

    For their example the ring oscillator running at 170kHz is designed on SilTerra C18G, a 0.18um CMOS process. The circuit consists of a current reference, an oscillating core and a level shifter. There are about 60 transistors in the circuit, including the current reference and trimming. This size design typically takes 2 or 3 days of work to adapt to a given specification. There are a number of knobs in the design that offer the necessary flexibility, but they also offer a potentially complicated design space – especially after variation and environmental factors are accounted for.

    Chipus in one of their examples chose 4.5MHz as their target speed. They used WiCkeD’s deterministic optimization capabilities to modify the fval for the design. It took several iterations. Part of the process involved managing the temperature behavior because the bias current affects the operating frequency. Once the frequency was dialed in, they proceeded to optimize current (Itot). The WiCkeD software can optimize to the lowest current value that does not affect the ability to meet the other specifications for the design. The images below show the various steps of each optimization phase.

    Article: Variation-Aware Design: A Hands-on Field Guide-muneda-wicked-sizing-min.jpg


    Where this example moved away from conventional usage of their tool is with the addition of Python scripts to allow recursive iteration that used previous optimization results as the starting point for new versions running at different frequencies. An added feature of comprehensively covering the design space over a range of frequencies is that a Pareto curve can be produced showing possible operating points.

    Article: Variation-Aware Design: A Hands-on Field Guide-muneda-pareto-oscillator-min.jpg


    Chipus ran the algorithm to create a family of 7 oscillators that run from 140kHz to 9MHz. This was accomplished in approximately 2 days using a typical desktop workstation and 4 Spectre licenses. The Python code was not necessarily design specific, so applying this technique to other designs should be straightforward. This shows the power of combining advanced analog optimization tools and scripting create some very impressive results. It looks like the day of rapid customization of analog IP is closer than it might have at first seemed. For a complete write up on the utilization of WiCkeD, I suggest looking at the MunEDA website.

    There is also a tutorial about low power circuit optimization for IoT from the 30th IEEE System-on-Chip Conference 2017 that is close to this topic featuring Michael Pronath of MunEDA:

    Abstract:
    Designing circuits for enhanced IoT (Internet of Things) applications is one of the current growth driver for the electronics industry. Optimizing such circuits for lowest power consumption while maximize functionality and performance is key for successful implementation of such circuits in the IoT systems. IoT devices are diverse in nature but are typically constrained by limited power availability, limited area budget and the need for modularity of design. The burden of ultra-low-power budget unfortunately doesn't necessarily mean that other performance requirements are relaxed. The tutorial is therefore geared towards designers of IoT devices including sensors, MEMS, mobile devices, medical sensors, wireless communication devices, near field communication devices, energy harvesting designs, mobile devices, and wireless communication devices. It will focus on how automated circuit sizing and tuning methodologies can be used to enhance existing design expertise to reduce power consumption while trade-off with other circuit performances. Additionally it will be shown how features like circuit sensitivity analysis can be used for confirming design hypotheses. Using such a verification and optimization environment can help systematically and fully explore design's operating, design and statistical design space.