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  • ARM and Cadence IP Simplify IoT System Design and Verification

    Article: Sequential Power Optimization-cdns-arm-min.jpgAs the Internet-of-Things (IoT) markets mature, we are seeing the complexity of IoT systems evolve from simple routing functions that connect IoT edge devices to the cloud into more complex system of systems that manage the interaction between multiple sensor-hubs. IoT sensor-hubs and gateways not only take care of basic care and feeding of sensors, but they are also now evolving to do more data fusion, analysis and analytics local to the edge devices. Doing this can decrease response time of the overall system while also reducing the amount of raw data that must be sent into the cloud.

    To do this type of work, IoT SoCs are becoming quite complex and include heterogeneous architectures containing multiple cores and GPUs, each of which have specialized capabilities to turn sensor data into information that can be used by cloud-based applications. These systems must manage shared local memory between processors and they must deal with multiple communications standards and protocols to talk to both the sensors and the cloud servers.

    Designing and verifying these types of SoCs from scratch could be a daunting task but I was pleasantly surprised by a demonstration at this yearís Design Automation Conference (DAC) that showed how far the industry has come to help designers tackle the problem. The demonstration was given by ARM and Cadence Design Systems, two companies who have partnered for several years to make SoC design easier. In fact, the Cadence-Heart-ARM graphic came from a SemiWiki article written by Paul McClellan in 2014 where Cadence and ARM were already working together on this topic.

    The point of the DAC2017 demonstration was to show designers how quickly and easily they could customize and verify a new IoT design using predefined platform IP from ARM and Cadence. Designers were presented with ARMís CoreLink SDK-200 System Design Kit which is a configurable platform comprised of one or more ARM Cortex-M33 cores, system memory, Cordio Radio IP, ARM Trustzone CryptoCell IP, AHB5 interconnect logic and any number of standard communications protocols and interfaces to communicate with different sensors and actuators.

    Article: Sequential Power Optimization-corelink-min.jpgThe demonstration started with several peripherals already pre-assembled into a system (5 from Cadence IP and one from ARMís IP catalogue). Designer attending the demonstration were tasked with adding a GPIO interface to the system and were timed to see how long it would take them to do the task.

    The idea was to get people to try the flow and see how long it would take them to add and configure a GPIO interface into the system and then verify they did it correctly using the Cadence Verification Workbench tool suite. ARM and Cadence walked me through this and I was amazed to see that with the use of ARMís Socrates development environment, a standard GPIO interface could be easily added to the IoT platform with literally only a couple minutes configuration work done by the designer. Socrates takes care of the rest by automatically generating all the necessary RTL code to make the connections to the ARM AHB5 interconnect fabric.

    Article: Sequential Power Optimization-iwb-min.jpgThe Cadence guys then jumped in and showed me how they can take the output of ARMís Socrates software and feed it into their Interconnect Workbench to automatically generate a UVM test bench for the entire system complete with Verification IP (VIP) for not only the ARM IoT platform (and all its constituent pieces) but also the GPIO block that had just been added. The generated test bench included test features needed to ensure the system was correctly connected. Within 5 minutes the full test bench was up and running enabling the designer to be able to start running both detailed functional tests as well as a suite of regression tests that could be used anytime new changes were added to the system.

    From scratch, this would have taken a large team of people multiple months to pull together the system and all the test benches required to test it. While I didnít run the actual tools, there were several people at DAC who did go through the full exercise at both the ARM and Cadence booths and from what I was told, some of the best times to complete the exercise were in the sub 5-minute regime. I've had days that I can't even log into my system in that amount of time. Obviously this was a demo, yet it spoke volumes to the power of having well architected and tested predefined platforms from which to start your design customization. I was certainly impressed.

    ARM and Cadence were quick to point out that the IoT design kit is only one of many different end-application platforms on which they have jointly worked and that the platform-based methodology they are espousing is generally applicable across many different types of SoC designs. And as noted earlier, this solution didnít just pop out of thin air. It is the fruit of many years labor by both ARM and Cadence working collaboratively to create the necessary software infrastructure that allows designers to functionally combine IP blocks at a higher level of abstraction and then automatically configure the logic and test benches to ensure a correct-by-construction implementation. This is a big leap forward for designer productivity as it allows designers to focus on customizing and verifying functionality that meets their end application needs as opposed to spending weeks or months manually making interface connections and writing test benches that may or may not verify their work.

    With the advent of the IoT market and the evolving nature of the SoCs needed to implement IoT systems, it looks like ARM and Cadence couldnít have fielded their joint solution at a better time. This kind of innovative cooperation is what separates true solutions providers from simple IP and tool providers.

    See also:
    ARM IoT Solutions
    Cadence SoC Interconnect Verification Solution