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  • Design Rule Development Platform @ #54DAC!

    While some might have expected the exponential growth in design rules number and complexity to cool down a little, it looks as if these are only heating up more. The multiplicity of technology nodes, lithography options, , fundamental technology options (Bulk, FD-SOI, FinFET), different process flavors and specific applications, have made design enablement and design rules in particular an even more painful issue than it used to be.

    Sage-DA addresses this problem in a systematic way with iDRM, a complete end-to-end integrated Design Rule Management System. iDRM encompasses all steps of design rule development, from design rule capture by the process integration team to the delivery of a compiled and verified DRC deck that accurately matches and represents the design rule intent.

    The system significantly shortens the turnaround time of every PDK release, reduces the engineering effort and most importantly - maintains consistency and eliminates errors.

    The benefits of automation are apparent and the value in this case is enormous, since the cost of mistakes and delayed delivery is so high. However at the same time, automation can sometimes seem disruptive and intimidating and therefore not always quick to adopt. To facilitate a smooth and easy adoption of this new automation technology, Sage-DA has developed new features in the new iDRM system, which it will show this year at DAC.

    The system puts an emphasis on interface and integration with existing tools and environments, so that iDRM can be easily integrated into current technology development and enablement flows. It includes features such as:

    - Reading from and synchronizing with design rule spreadsheets. This enables automatic import of design rules into the iDRM system and instant synchronization of any rule update or new rule additions.
    - Using pre-defined rule templates. Most rules can be entered using a pre-defined rule type (or template) , this makes adding rules and rule editing quicker, easier and more consistent.
    - Extraction of design rule values from existing layouts so that they don't need to be typed in manually
    - Compilation of sign-off DRC code. Users can automatically generate DRC code for their signoff DRC tool by using rule templates.
    - QA and test of DRC code by automatic generation of pass/fail patterns with coverage measurement

    Article: How much SRAM proportion could be integrated in SoC at 20 nm and below?-idrm_2017_1.jpg

    Early customer deployment successful experience

    The significant investment Sage has put into the new upgraded system is already paying off for Sage and its customers. Sage mentioned two recent successful customer use-cases:

    1. An advanced technology semiconductor company uses iDRM to enforce consistency and to automatically generate 3rd party DRC code for its most advanced node technology (below 14nm). The results are faster turnaround times for DRC runsets and ensured consistency.

    2. Another semiconductor company develops multiple and diverse IC technologies for different markets and applications. It uses iDRM to qualify and validate their DRC signoff runsets, using the DRVerify tool of iDRM. DRVerify automatically generates high coverage QA test layout to test the DRC runset. Using the system, the users were already able to detect errors and gaps in their existing signoff DRC runsets, which until then were traditionally coded and qualified.

    Sage-DA will demo the new system and functionality at DAC in Austin next week. You can find them at booth #513 or see http://www.sage-da.com/news/1706-sage-dac2017.html