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  • Safety EDA

    It takes courage and perhaps even a little insanity to start a new EDA venture these days – unless you have a decently differentiated value proposition in a hot market. One company that caught my eye, Austemper, seems to measure up to these standards (though I can't speak to the insanity part). They offer EDA tooling specifically around safety and span from safety analysis (FIT and fault metrics), through safety synthesis to safety verification.

    Article: How much SRAM proportion could be integrated in SoC at 20 nm and below?-austemper-tool-suite-min-jpg

    Safety verification through fault injection is offered by bigger players but even here Austemper may have an angle to differentiate their offering. What intrigues me is that safety could quite likely evolve into a specialized in-house design service, like test or power, where experts may be open to end-to-end flows rather than a collection of in-house and vendor point tools. Which would play well to this kind of solution.

    The company offers four tools in three functional areas, starting with SafetyScope, which computes the failures in time (FIT) and fault metrics for a design. The FIT calculation is based on a rather involved equation from the IEC 62380 model, where inputs can come from IP suppliers/other experts and can be augmented with user input. A safety plan can also be fed into this stage. Apparently, analysis can be “out of context” in which case it is essentially static or it can be “in context” in which case it can take usage data into account. The output of this stage is metrics across the design for FIT rate and diagnostic coverage required to get to target ASIL levels. This stage also generates fault-injection points to be used in the verification phase.

    Safety hardening is handled by Annealer for big changes like duplication or triplication of blocks and Radioscope which does similar things at a finer-grained level (e.g. register banks). Here they replicate and inject logic to implement hardening. In Annealer selected logic can be automatically duplicated with comparison checks inserted to detect mismatches or selected logic can be triplicated along with majority voting. In Radioscope, similar automated replication occurs with parity checks for duplication and ECC for triplication. Radioscope can also add protocol checks to critical FSMs for legal states and legal transitions.

    The final tool in the flow is Kaleidoscope which does fault simulation based on injected faults, as is generally required as a part of verification for safety-critical designs. Here they use their own fault simulator to simulate behavior for faults injected into the gate-level design but with wrinkles. First, they can take a VCD developed by any simulator as a starting point. It seems they also intelligently limit each fault simulation, in time and in design scope, to limit run-time. They can also run many injected faults in parallel to classify a large number of faults as masked or failed-state in a single run.

    On customers, there’s the usual problem of not being able to reveal names, but Sanjay Pillay, the CEO, did tell me that they have been working for a year with a supplier to a tier-1 customer, who have now taped out. They are now working on their second customer. This sounds like an interesting company with some real-world (if not shareable) validation.

    Austemper was founded in 2015 and is based in Austin. Sanjay previously led SoC development organizations at a variety of companies, including development for tier-1 companies. He also served as functional safety consultant in some of these roles. You can learn more about the company HERE.