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  • ARM's (Back!) in FD-SOI. NXP's Showing (Real!) Chips.

    “Yes, we’re back,” Ron Moore, VP of ARM’s physical design group told a packed ballroom at the recent FD-SOI Symposium organized in Silicon Valley by the SOI Consortium. FD-SOI gives you a silicon platform that’s highly controllable, enables ultra-low power devices, and is really good with RF, said Ron Moore during his presentation, Low-Power IP: Essential Ingredients for IoT Opportunities.

    ARM’s worked with Samsung’s 28FDS FD-SOI offering comparing libraries on bulk and FDSOI, for example, and came up with some impressive figures.

    With the foundry partners and wafer providers in place, ARM is now asking about which subsystems are needed to fuel FD-SOI adoption. Ron recognizes that the ARM IP portal doesn’t yet have anything posted for FD-SOI, but they know they need to do it.

    But the bottom line is that if you’re designing in FD-SOI, ARM will help, he said during the panel discussion at the end of the day. He also called on the SOI Consortium to help with IoT reference designs and silicon proof points.

    Debugging is not free!!-arm_fdsoi_soiconsortium.jpg

    ARM worked with Samsung to compare libraries on 28nm bulk vs 28nm FD-SOI, and came back with compelling results. (Courtesy: ARM, SOI Consortium)


    An audience member asked about FD-SOI and low-cost manufacturing of IoT chips during the Q&A. Ron replied that we should be integrating functionality and charging a premium for IoT – this is not about your 25-cent chip, he quipped.

    NXP – Biasing & ULP

    Geoff Lees, SVP & GM of NXP’s Microcontroller business gave an excellent talk on their new i.MX 7 and 8 chips on 28nm FD-SOI. (For in-depth explanations about why they chose FD-SOI, see NXP VP Ron Martino’s pieces from last year in SemiWiki.)

    The i.MX 7 ULP has been sampling to customers over the last six months, the i.MX 8QM is ramping, and the i.MX 8QXP, 8Q and 8DX are next. You might ask how they're getting so many chips out in such a short span of time? This is important: each of these chips is optimized for specific applications using biasing. He explained that a majority of the design of each chip is hard re-use, and the subsystems can be lifted and dropped right into the next chip in the series. Power consumption and leakage are a tiny fraction of what they’d had been in previous generations, pushing ultra low power (aka ULP) to new levels.

    He pointed out that with FD-SOI, it’s easy to optimize at multiple points:
    1. in the chip design phase,
    2. in the production phase. and
    3. in the use phase.


    They can meet a wide range of use cases, precisely targeting for power usage. FD-SOI makes it a win-win: it’s a very cost effective way to work for NXP, plus their customers today need that broader range of functionality from each chip.

    He gave a tip-of-the-hat to Professor Boris Murmann of Stanford, who’s driving mixed signal and RF into new areas, enabling high-performance analog and RF integration. He ended by citing Soitec Chief Scientist Bich-Yen Nguyen, who said: if half your chip is analog and/or RF, the future is very bright indeed for FD-SOI.

    Get These Presentations

    Briefly, here are highlights from some of the other presentations.

    Synopsys: John Koeter, VP of the Marketing Solutions group talked about some of the IP they've done for the Samsung and GlobalFoundries FD-SOI offerings. But there’s a lot they’ve done with partners he couldn’t show because it’s not public. In terms of tools and flows, it’s all straightforward.

    Dreamchip: COO Jens Benndoorf presented New Computer Vision Processor Chip Design for Automotive ADAS CNN Applications in 22nm FDSOI. One application for these chips (which taped out in January) will be “digital mirroring”: replacing sideview mirrors with screens. Why hasn’t this been done before? Because LED flickering really messes with sensor readings – but they’ve mastered that with algorithms. The chip will also be used for 360o top view cameras and pedestrian detection. They’re using Arteris IP for the onchip networking, and implemented forward body bias (FBB). But cost was a huge motivator: designing their new chip in 22nm FD-SOI was 2.5x less expensive than designing it in FinFET would have been. The reference platform they created for licensing has generated lots of interest in the automotive supply chain, he said.

    Debugging is not free!!-dreamchip_fdsoi1.jpg

    Dreamchip is using Arteris IP for their ADAS chip, which is fabbed by GF in 22nm FD-SOI (Courtesy: Dreamchip, SOI Consortium)


    GreenWaves: With a budget of just three million euros, GreenWaves is porting their high performance, ultra-low power IoT applications processor from bulk to FDSOI. The RISC-V chip leverages an open source architecture (which CEO Loic Lietar says customers love) and targets smart city, smart factory, security and safety applications. As such, it needs to wake up very fast using just microwatts of power – a perfect match for body biasing in FD-SOI.

    Debugging is not free!!-greenwaves_fdsoi.jpg

    Greenwaves expects big power savings in their move to FD-SOI. (Courtesy: Greenwaves, SOI Consortium)


    Leti: CEO Marie-Noelle Semeria said the main two drivers they’re seeing in the move to FD-SOI are #1: low power (a customer making chips for hearing aids can cut power by 8x using body biasing, for example) and #2: RF (with Ft and Fmax performance that “…will be hard for FinFET to achieve”). Her talk dealt largely with roadmaps. Leti knows how to pull in all kinds of boosters, and is finding that RF performance is still excellent at the 10/7nm node. They’ve developed a low-power IoT platform with IP available for licensing. Other recent FD-SOI breakthroughs by Leti include: demonstration of a 5G mmW 60GHz transceiver developed with ST; the first 300mm Qbit, opening the door to quantum computing; a photodiode opening the door to a light-controlled SRAM; and a new 3D memory architecture leveraging their CoolCubeTM that they’re working on with Stanford.

    IBS: There “will be war in the year to come” at the 22nm node, predicts CEO Handel Jones, as all the big foundries take aim. He sees FD-SOI as the best technology for RF, ULP and AMS, and notes that there’s a huge market for it. He also said China made the right decision to support FD-SOI, and will come out ahead in 5G.

    And finallly, as I was the moderator, I can vouch for the liveliness of the panel discussion at the end of the day. ARM, GF, Invecas, Soitec, Synopsys, Verisilicon and Sankalp participated, and IP availability was a big theme. While acknowledging that some gaps still exist, everyone agreed that they’re quickly being filled. As to the FD-SOI wafers, Soitec VP Christophe Maleville confirmed that they are readily available and that the wafer manufacturers are seeing excellent yields.

    BTW, these symposia and related tutorial days will also be held in Japan in June (just before VLSI) and in Shanghai in the fall. Most of the presentations are posted (and freely available) on the SOI Consortium website. But for now, it was another really good day in Silicon Valley for the FD-SOI ecosystem.