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  • It's Time to Stop Thinking in Two Dimensions

    The first transistor was made of two electrodes, held in place by plastic, making contact with a piece of doped germanium. Ever since then, devices and their packaging have been performing a complicated and oftentimes intricate dance. Single transistor devices became integrated circuits, and along the way separate ICís were connected together inside of multichip modules (MCMís). With the large growth in transistor counts of new generation ICís, MCMís became less frequently used. However, just as so many things run in cycles the idea of combining separate IC die into a single unit has come of age again.

    The buzz around so-called 2.5D and 3D ICís started in earnest well before 2011. However, back then it was easily filed away as an exotic solution looking for a problem. Nevertheless, just as so many things take time to mature, 2.5D ICís have recently become mainstream. However, it has taken major initiatives by a wide range of players to bring the technology to fruition.

    Letís look at some of the motivations driving the growth of 3D IC technology. Yield is a big factor. A yield issue on a large die can be very expensive because you have to throw away the whole die. Xilinx among others decided it made more sense to combine smaller die into a single part. A failure on a single smaller die only means losing a smaller element, not the entire, expensive, larger die.

    Article: Chip On Wafer On Substrate (CoWoS)-2.5d-advantages-min.jpg


    Technology to combine the dies to make a single part was needed to make this possible. This is why interposer technology came into play. Silicon or organic substrates can be used to provide compact and high performance connections between the separate dies, which are arranged next to each other in a planar configuration.

    This brings us to the next motivating factor Ė increased density. GDDR5 memory has been a work horse for a long time, but there is a need for lower power and higher throughput. This is where HBM comes in. It offers stacked memory die with benefits in power, density and throughput. Stacking dies and the dense interposer interface for HBM represent a big leap forward in packaging complexity.

    Another big motivating factor for 2.5D integration comes from widely different development and design requirements for different functions in an IC device. The best example of this comes from networking applications where the core engine needs to be on the latest node, and the SerDes can stay back on earlier proven and costs effective technologies. Itís much easier to move data to a separate SerDes chiplet than to incorporate a SerDes into the main die when a new SerDes would need to be developed at a node like 16 or 10nm. Furthermore, it is less likely there will be noise and isolation issues with the SerDes on its own die.

    2.5D and 3D technology is like a smorgasbord of complex components. Selecting the right combination of memories, IP blocks, interposer technology, inter-chip communications, final package and assembly method require careful consideration. While going to 2.5 or 3D might be necessary to create higher performing and competitive products, wading into the technology requires a great deal of knowledge. Whatís more, suddenly there are a large number of elements in the supply chain. Coordination among them is critical to success.

    It turns out that eSilicon has been involved with 2.5D IC design and manufacturing for a long time. Patrick Soheili, eSiliconís VP of Business and Corporate Development, shared with me some of their experiences creating test chips using 2.5D and 3D technology. They chose different technical approaches for each of them. See the diagram below for an overview of the technologies used.

    Article: Chip On Wafer On Substrate (CoWoS)-esilicon-test-chips-min.jpg


    In March of this year they announced a production chip developed using a 14nm ASIC, 28G SerDes and HBM2. This successful tape out also included eSilicon IP blocks for TCAM, EVGPIO and embedded memories. eSilicon combined internal and external IP and handled the details of design implementation as well as the logistics involved in producing tested functioning parts. This is quite an accomplishment. As Patrick likes to point out, the devil is in the details. Some of the key points they have addressed include design for manufacturing (DFM), signal integrity, thermal integrity and management, warpage and coplanarity analysis and specification.

    Article: Chip On Wafer On Substrate (CoWoS)-2.5d-technical-issues-min.jpg


    eSilicon has put an excellent summary of the options available for 2.5D and 3D design implementation and packaging on their website. It includes an over view of the HBM design elements they offer, including PHY. It also details their partners for 2.5D and 3D designs.

    Just as the leap from solitary junction devices to integrated circuits required a significant evolution, so too the coming of age of 2.5D ICís has involved a lot of learning from experience. Similarly, the benefits of these technologies will push product capabilities to new levels.