The EDA & IP industry enjoys high growth for the Design IP segment, but a detailed analysis tool is missing. IPnest will address this need in 2017, expecting the IP vendors’ contribution! If we consider the results posted last March by the ESD Alliance, the EDA (and IP) industry is doing extremely well, as the global revenue has grown in Q4 2016 by 22% compared with Q4 2015! If we zoom to the “Design IP” category, the 22% growth rate is online with the industry and the most significant information is the confirmation that the “Design IP” is now confirmed to be the largest category. The “CAE” category used to be by far the #1 for years, until 2015 as you can see on the graphic below.
When you see the slope of the Design IP curve in light blue during the last 3 to 4 years, you realize that the Design IP category will stay #1 in the future. As we all need facts, I have calculated the CAGR for 2010 to 2016: The Design IP category has grown with a 16% CAGR, when the next category (CAE) has grown with a 7% CAGR. All is good for Design IP, except that the industry miss a detailed analysis tool, like the former “Design IP Report” released by Gartner up to 2015. IPnest will launch this type of report in April 2017, covering the Design IP market by category for 2015 and 2016.
The obvious difference between the Design IP segment and any other EDA category is the business model, based on up-front licenses and royalties (even if only certain vendors ask for royalties). The royalty part of the revenues should be clearly identified, and two main categories defined: IP License and IP Royalty.
To better understand the Design IP market dynamic, we need to segment this market into categories:
· Microprocessor (CPU)
· Digital Signal Processing (DSP core)
· Graphic Processing (GPU)
· Wired Interface IP
· Wireless Communication IP
· SRAM Memory Compilers (Cells/Blocks)
· Others (OTP, MTP, Flash, XRAM) Memory Compilers
· Physical Library (Standard cell & I/O)
· General Purpose Analog & Mixed Signal
· Infrastructure IP (NoC, AMBA)
· Miscellaneous Digital IP
You can download the pdf version of the Excel spreadsheet at the bottom of this article
… or contact me: firstname.lastname@example.org
If we only consider the large, well-known IP vendors like ARM, Imagination, CEVA, Synopsys, Cadence or Rambus to measure the Design IP market, we will probably reach 80% of the effective market size. But the remaining 20% are made of a multitude of companies and some of them are very innovative, maybe designing the next big function that all the chip makers will integrate tomorrow. We need IP vendors to contribute by sharing their revenues, and we need all of them to participate!
Like the EDA market, the IP market history has been marked by acquisitions. Back in 2004, the acquisition of Artisan by ARM for almost $1 billion has been like a thunderclap (Artisan revenue was about $100 million). When you look at the way Synopsys has built their IP port-folio, it was through the successive acquisitions of InSilicon, Cascade (PCI Express controller), Mosaid (DDRn memory controller), the Analog Business Group of MIPS Technologies or the largest, the acquisition of Virage Logic in 2009 for $315 million (logic libraries and memory compilers). The “Design IP Report” can also be an efficient tool for the small IP vendors to get visibility and for the large one to complement their port-folio through an acquisition…
Like EDA, the IP market is not monolithic, but made of various IP categories. Each category follows its own market dynamic and if you want to build an accurate IP market forecast, you will have to consider each category individually, project the specific evolution and finally consolidate and calculate the global IP market forecast. This approach works reasonably well. For example, for the Interface IP segment, made of various protocols (PCIe, USB, MIPI, and many more), IPnest has started to build a 5 year forecast in 2009, and did it every year. We could measure the difference between the forecast and the actual results for the first time in 2014 and I am proud to say that the forecast was accurate within +/- 5%, and this error margin has stayed the same every year.
If you, as an IP vendor, think that you need to benefit from an accurate report (the “Design IP Report”) and if you expect to see some accurate forecast of the IP market, you need to contribute and share your IP revenues!
Eric Esteve from IPNEST
Don’t miss the “IP Paradox” panel during the DAC 2017, organized by Eric Esteve and moderated by Dan Nenni:
The IP Paradox: Growing Business Despite Consolidations