Nodes must die
I have written several articles comparing process technologies across the leading-edge logic producers - GLOBALFOUNDRIES, Intel, Samsung and TSMC. Comparing logic technologies to each other requires a metric for process density.
For many years, the industry has described processes based on "nodes". Originally node was equivalent to the gate length but over time nodes have become disconnected from any physical features on the process. Figure 1 illustrates gate length versus node for Intel and TSMC processes. As you can see from figure 1, down until 500nm the gate length and node were the same, then from 500nm to 32nm the gate length was smaller than the node until as FinFETs were introduced the gate length became larger than the node. In addition to a disconnect between the node and physical features the use of node names has differed by company.
Figure 1. Node versus gate length
To address this issue ASML plotted the minimum metal half-pitch multiplied by the contacted poly half pitch versus node for many companies and nodes. As will be discussed further below, minimum metal half-pitch or pitch and contacted poly half-pitch or pitch are key elements in the size of standard cell used to design logic devices. I have also performed and published a similar analysis using pitches, see figure 2. My analysis includes 54 processes from 130nm to 7nm from 12 companies (this graph includes updated Intel pitches disclosed yesterday).
Figure 2. Node versus minimum metal pitch multiplied by contacted poly pitch
This analysis still ignores a third element of standard cells, track height. The height of a standard cell is the minimum metal pitch (MMP) multiplied by the number of tracks, see figure 3. The width of a standard cell is typically characterized by contacted poly pitch (CPP) but even that is not a complete description as we will see later. Figure 3 illustrates a 7.5 track standard cell.
Figure 3. 7.5 track standard cell
As scaling of MMP and CPP has gotten more difficult there has been increasing attention paid to track height and design-technology-co-optimization (DTCO). New technologies are being introduce with smaller track heights as part of their density improvement process. For example, at 16nm TSMC has a 7.5 track cell and at 7nm they are reported to be introducing a 6-track cell. There are a lot of issues around reducing track height because as track height is reduced you can't fit as many fins, so for example for a 9-track cell there would typically have 4 fins per transistor but at 7.5-tracks only 3 fins per transistor will fit. Less fins per transistor reduces drive current unless you compensate by some type of process optimization such as taller fins.
I have been thinking for some time now that I need to incorporate track height into my comparisons and I have been considering plotting MMP x Tracks x CPP vs node as a new approach. But then roughly two weeks ago I had a conversation with Mark Bohr about a metric for process density that Intel wanted to propose and Mark pointed out that there are secondary design factors that affect cell width. This was really driven home to me yesterday when Kaizad Mistry presented on Intel's 10nm technology and showed the change from a double dummy gate to a single dummy gate and reported it provided ~20% scaling benefit! Figure 4 illustrates the single versus double dummy gate.
Figure 4. Single dummy gate versus double dummy gate.
The transition from double dummy gates to single dummy gates reduces cell width in a way that isn't captured in CPP.
Intel is proposing a transistor density metric that is based on actual standard cells widely used in logic processes. Specifically, a 2 input NAND gate would be weighted at 60% and a complex scan flip-flop cell would be weighted at 40%. The resulting calculation produces a single transistor density number that can be used to compare processes. Figure 5 illustrates the proposed metric. I hadn't encountered this before but Mark said this is an old metric that had been abandoned.
Figure 5. Proposed logic transistor density metric.
Technically I think this is a good metric to provide fair comparisons between logic processes for density. My concern about this metric as I expressed to them is the availability of the data needed to calculate the density of a process when it is first disclosed. Certainly, once a process is in production all of the data needed for this metric can be measured but unless the metric is adopted by all four leading edge logic producers as analysts we will be forced to work with the metrics we can get. Typically, MMP, CPP and to a lesser extent track heights are available around the time that a process is first described publicly. I have suggested to Intel that it would make sense to get a neutral organization such as the IEEE to make a metric like this a standard to insure it is adopted.
There has been a lot of confusion in the industry about how different companies process densities compare. Samsung and TSMC are both ramping "10nm" processes with "7nm" planned to ramp by the end of 2018. Intel is going to ramp their "10nm" later this year and some people have suggested this indicates that Intel is falling behind. Intel's 10nm process is denser than Samsung's or TSMC's 10nm processes and similar or superior to Samsung's and TSMC's 7nm processes. A single comprehensive metric would make this much clearer. I will be discussing how different companies leading edge processes compare based on the new information available on Intel's 10nm process in a separate blog.
Moore's law lives!
During Stacy Smith's presentation he made a strong statement that at least for Intel, Moore's law lives on.
Since it is so often incorrectly quoted, including ironically by Smith yesterday, lets return to the original 1965 Electronics magazine article where Moore first made his observation.
"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year"
Moore's law therefore lives on if costs are coming down for "components" of which transistors are the most common on integrated circuits.
Figure 6. illustrates Intel's transistor density per year and shows a doubling roughly every two years. The interesting thing to note here is that although node transitions have slowed down, the scaling per node has increased delivering the same rate of scaling per year.
Figure 6. Intel's transistor density trend.
Figure 7 illustrates Intel's cost per wafer, transistor density and transistor cost by node. Another interesting observation here is that although cost per wafer has accelerated due to multi-patterning the increased rate of scaling has more than offset the wafer cost to deliver better than the historical trend cost improvements.
Figure 7. Intel's cost trend.
In case you think Intel is the only company delivering cost per transistor improvements, figure 8 illustrates my modeling results for TSMC's cost trend.
Figure 8. TSMC's cost per transistor trend.
As you can see the projected cost improvements are very similar to what Intel is disclosing.
I do need to note here that these figures are manufacturing costs only. Design costs are going up rapidly at each new node and are limiting the number of design that can afford to take advantage of these cost saving, but for high volume products Moore's law is very much alive.
I will follow this blog up with another blog discussing the technology disclosures Intel made yesterday and providing some comparisons to other company's technologies.