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  • Cadence Expands Integrated Photonics Beachhead

    Article: ICCAD at 30: Alberto Looks Back and Forward-beach-jpgIn November of 2016, I made a bold statement that October 20, 2016 would stand as a watershed day in integrated photonics. The reason for this claim was that GLOBALFOUNDRIES proclaimed that integrated photonics was real and here to stay. The same week I wrote an article about Cadence Design Systems securing a photonic beachhead when they, Lumerical Solutions and PhoeniX Software held their first joint training class for over 70 prospective customers on a new fabless integrated electronic-photonic design automation (EPDA) flow. It’s now five months later, and I am more convinced than ever of my statement about that October. Several things have happened in those short five months.

    First, I’ve had the chance to be in a lot of conversations with potential users of the triumvirate EPDA flow. Interest has been high from the fabless community, adding weight to GLOBALFOUNDRIES’ proclamation about integrated photonics. So far, feedback from users has been very consistent. They are looking for a production-worthy design flow that promises to bring a much-needed formalism to electronic-photonic circuit design. The integration of photonic and electronic simulations along with the formalism of a schematic-driven layout flow seems to have answered a need that has heretofore been missing in photonic design. The fact that users are looking for such formalism says much to me about their seriousness in making production electronic-photonic designs.
    Article: ICCAD at 30: Alberto Looks Back and Forward-cds-gui-jpg
    Second, users quickly noted the improved productivity they can get in the layout phase of the design when using Cadence Virtuoso in combination with the PhoeniX Software tools. In many ways, this even surpasses the productivity boost users saw when adopting automation for analog IC layout as photonic curvilinear shape generation can be very time-consuming if not automated. The joint EPDA flow goes a long way towards improving the engineer’s life when it comes to doing photonic layouts.

    Third, is that Cadence, PhoeniX and Lumerical are now planning to expand the flow into the 2.5D, 3D and SiP (system in package) domain. This is a major and important step as most high-volume applications will want to take advantage of silicon-photonics manufacturing cost advantages. These solutions will require photonic light sources, amplification and detection and that means working with III-V materials like InP or InGaAs in combination with the silicon photonic-IC (PIC). Si-based PICs will also need to be tightly tied to both digital and analog electrical ICs. While there are many ways to put these solutions together, one of the most obvious and near-term is to put them together as a SiP using an interposer capable of both electronic and photonic die-to-die and die-to-package connections.

    Article: ICCAD at 30: Alberto Looks Back and Forward-psmc3-jpgThis is a major undertaking for a fabless company as it requires a significant investment in design tools and very good relationships with ecosystem partners. Consider, however, that except for the photonics part, Cadence has had a flow for some time now to enable heterogeneous electronic SiP designs, and they have been working with several partners in this area. With the new EPDA flow, much of the work and associated risk for a heterogeneous electronic-photonic EPDA-SiP design flow has already been addressed. Simulation of electronic SiP designs is already handled in Cadence’s Virtuoso ADE environment and likewise, with the integration of Lumerical’s INTERCONNECT circuit simulator, so too is simulation of the EPDA-SiP design. All the necessary plumbing exists. Similarly, layout of an electrical-optical interposer with waveguides can also be done in Virtuoso using the combination of Virtuoso and PhoeniX Software’s OptoDesigner.

    As a quick review, here is the current Cadence portfolio for 2.5D, 3D and SiP design.Article: ICCAD at 30: Alberto Looks Back and Forward-cdns-sip-jpg
    • OrbitIO Interconnect Designer: Used for die-to-die and die-to-package connectivity planning.
    • Genus Synthesis Solution and Modus Test Solution: Used for generating design-for-test (DFT) logic of the electrical portions of the SiP.
    • Innovus Implementation System and Physical Verification System (PVS): Used for digital design implementation and verification. Innovus has a plugin that provides for through-silicon-vias (TSVs) and micro-bump placement while PVS can do DRC and LVSI checking across multiple dice in the package.
    • Virtuoso ADE and Spectre: Used for simulation of electronic and photonic systems in combination with Lumerical’s INTERCONNECT photonic circuit simulator.
    • Virtuoso: Used for layout of analog and photonic designs in combination with PhoeniX Software’s OptoDesigner layout tool. Virtuoso also supports TSVs and the mapping of memory die bumps to logic die.
    • Cadence SiP Layout: Enables 3D displays of both silicon and package layers for multi-die integration.
    • Quantus QRC Extraction Solution: Enables parasitic extraction of interposer metal traces as well as TSVs and micro-bumps.
    • Tempus Timing Signoff: Enables static timing analysis and signal integrity checks across multiple die and power domains.
    • Voltus IC Power Integrity Solution: Enables multi-die, 2.5D, 3D and SiP power analysis.
    • Sigrity PowerDC: Voltus can forward information to Sigrity which can then determine a temperature distribution map based on power consumption data. This power map can then be provided back to Voltus for temperature dependent IR drop analysis.

    Article: ICCAD at 30: Alberto Looks Back and Forward-heatmap-jpgSo, what is still missing for the EPDA-SiP flow? Board-based photonics is well on its way to being part of the overall solution. And, it appears that it would make sense to enable designers to account for heating effects on temperature-sensitive PIC devices caused by hot electrical ICs in a SiP. One last big issue that needs to be tackled by not just Cadence but the entire industry is what design-for-test looks like in photonics and heterogenous electronic-photonic SiPs.

    Nonetheless, I repeat my opinion that October 20, 2016 was indeed a watershed event for integrated photonics as it saw the launching of a very comprehensive fabless EPDA flow that will likely be host to many heterogeneous electronic-photonic designs to come. And, from what we are seeing now, it appears that the flow will become even more comprehensive, allowing Cadence to expand their integrated photonic beachhead.

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