I recently had the opportunity to review this question with Abhijit Abhyankar, Vice President of Silicon Engineering at Flex Logix, Inc., providers of embedded FGPA (eFPGA) IP. For silicon validation, they have the added complexity that the end functional application is not fixed, but rather defined in the field.
We talked about some of the deficiencies commonly present in current silicon-proven IP methodologies.
- packaging technology for the silicon IP
The package parasitics strongly impact the measured performance of the shuttle IP die. "You can't just add some general-purpose input receiver and output driver I/O cells (GPIO) to the shuttle testsite design, and expect to adequately characterize high-performance IP.", Abhijit highlighted. "You have to add an architecture around the IP on the testsite, to provide stimulus and capture results at-speed, with a synchronous interface at the IP boundary."
- internal IP voltage
Hard IP designs include technical specifications for the required supply voltage at the IP power pins. The SoC customer is expected to provide a global supply distribution network that meets a maximum local voltage drop requirement. Applying a voltage to the shuttle package pins for validation does not reflect the local voltage present at the IP.
- internal IP temperature
Similarly, the IP specification includes the temperature range over which functionality is validated. Specifically, this is the device junction temperature, which is a function of the ambient, the thermal resistance between package/die attach/substrate, and the IP switching activity.
The customers for the FlexLogix eFPGA IP span the gamut, from very low-power IoT end products to high-speed network communications to mil-aero (please refer to the recent DARPA announcement here). As a result, the environmental voltage and temperature extremes required by customer applications are pushing the technology, whether it be 40nm, 28nm, or 16nm.
Abhijit described the approach that was taken to develop their shuttle design. "We needed to develop a validation strategy for the eFPGA IP that enabled us to accurately measure performance, as well as local voltage and temperature. We collaborated with other IP partners to integrate sensors on the validation testsite. Performance validation necessitated integrating a precision PLL to provide an internal, programmable (low skew) clock distribution. SRAM arrays surround the eFPGA IP, to provide the source test data and capture responses."
The architecture for the eFPGA characterization testsite is illustrated in the figure below.
Note the presence of several eFPGA IP blocks on the shuttle design, reflecting the various eFPGA array types to be validated with device threshold voltage combinations to address customer power/performance applications. Voltage and temperature sensors are included around the IP blocks.
The ability to measure internal performance, while monitoring local voltage and temperature, is necessary but not sufficient to properly characterize an embedded IP block. The validation strategy requires applying environmental extremes, as well. Abhijit continued, "We partnered with package and board design firms, to develop a unique physical testbench. The eFPGA validation package is socketed to a board, which includes a fixture to attach an external thermal forcing source system." (Please refer to the figures below.)
The thermal forcing system enables characterization over the temperature extremes (and temperature cycles) to meet mil-aero and automotive specifications, which are measured directly on-die using the sensor IP.
We chatted briefly about the unique temperature inversion phenomenon at advanced process nodes, and thus the requirement to measure performance over the full temperature specification range.
Then, Abhijit blew me away with the following insight. "eFPGA IP is unique. Our customers are seeking to measure the performance of their specific algorithms, when programmed on the IP. We provide delay calculation and static timing analysis tool support, which predicts performance with high accuracy, using (corner-based) foundry PDF extraction models. Yet, the customers want to explicitly measure performance in silicon, at their facility, with their specific eFPGA netlist."
The validation strategy that Flex Logix has pursued for analysis also directly enables their customers to share the same PVT characterization approach at the customer's site (potentially using foundry shuttle split lots). The validation report from Flex Logix illustrates how the clocking, SRAM stimulus/capture, and voltage/temp sensors are used to measure internal IP performance. This strategy takes the notion of silicon-proven IP to the next level, where customers can readily conduct their own lab bench characterization procedures, on isolatable IP from a foundry test shuttle.
For eFPGA IP, I learned that lab bench-proven is a customer expectation. My discussion with the Flex Logix team got me thinking that their approach may indeed be required for other complex IP blocks at advanced process nodes, as well. IP providers may need to invest the time and resources to provide customers with the collateral to be able to pursue their own unique silicon validation methodologies.
For more info on Flex Logix embedded FPGA IP, please refer to the following link.