Six Reasons to Consider Using FPGA Prototyping for ASIC Designs

There's no doubt that programmable logic in FPGAs have transformed our electronics industry for the better. If you do ASIC designs then there's always the pressure of getting first silicon correct, with no functional or timing bugs, because bugs will cause expensive re-spins and delay time to market. ASIC designers on the leading edge of design complexity have been adopting an FPGA prototyping approach to improve their chances of first silicon success, and I wanted to list the top six reasons for using FPGA prototyping for ASIC designs:

1. Reduces risk
2. Shortens the design schedule
3. Enables early software development
4. Allows real time system verification
5. Boosts reliability
6. Increases design flexibility

I'll be attending and blogging about a webinar on this topic next week, Tuesday, March 21st, "The Role and Benefits of FPGA Prototyping in the ASIC Design Cycle", from 8AM to 9AM PDT.


Related blog - Webinar: FPGA Prototyping and ASIC Design

About the Webinar
This joint Open-Silicon and PRO DESIGN Electronic webinar, moderated by Bernard Murphy of SemiWiki, will address the benefits of FPGA-based prototyping in the ASIC design cycle, and the role it plays in significantly reducing the risk and schedules for specification-to-custom SoC (ASIC) development and the volume production ramp. Early software development and real time system verification, enabled by FPGA prototyping, offers a cost-efficient high-end solution that shortens process cycles, boosts reliability, increases design flexibility, and reduces risk and cost. The panelists will outline best practices to overcome technical design challenges encountered in FPGA prototype development, such as design partitioning, real-time interfaces, debug and design bring-up. They will also discuss the key technical advantages that FPGA-based prototyping offers, such as architectural exploration, IP development, acceleration of RTL verification, pre-silicon firmware and software development, proof of concept and demonstrations. They will also talk about its affect on performance, scalability, flexibility, modularity and connectivity.

Who should attend this Webinar
This webinar is ideal for hardware system architects, hardware designers, SoC designers, ASIC designers, and SoC firmware and software developers.

Moderator

Bernard Murphy – ModeratorBlogger
SemiWiki

Bernard is a blogger for SemiWiki, covering IP and SoC design. He has also written past blogs for EE Times and has contributed to Semiconductor Engineering as well. Prior to joining SemiWiki, Bernard served as CTO for Atrenta for 15 years.

Speakers

Philipp Ampletzer
Director of Sales and Business Development
PRO DESIGN Electronic GmbH

Philipp serves as Director of Sales and Business Development for PRO DESIGN Electronic GmbH in Germany. He has been with the company for over ten years, where he started as a project manager.


Sachin Jadhav
Technical Lead, Systems and Software Engineering
Open-Silicon

Sachin serves as Technical Lead of Systems and Software Engineering for Open-Silicon, where he manages the ASIC prototyping collateral operations. He has ten years of specialized experience in ASICs, architecture, embedded systems, debugging, embedded software, device drivers, communications protocols, shell scripting and kernel.

Related blog - Open-Silicon Update, 125M ASICs Shipped!

Webinar Registration
This webinar requires online registration here, so I hope to see all of you next week as we learn together about all of the benefits to FPGA prototyping for ASIC designs.