Logic chips are built up from standard cells. The width of a standard cell is the contacted poly pitch (CPP) and the height is the minimum metal pitch (MMP) multiplied by the number of tracks. Cells may be various numbers of tracks, for example 9, 7.5, 6, or 5 but as you reduce the number of tracks layout becomes more difficult and the number of fins that fit in the cell is reduced creating process challenges to maintain performance. Figure one illustrates a 9T4 cell with 9 tracks and 4 FinFETs per FET.
Figure 1. 9T4 Standard Cell.
Since the standard cell size is CPP x MMP x Tracks, CPP x MMP provides a good metric of process density.
The semiconductor industry has decades of history characterizing processes based on the "node". At one time the node was equal to the gate length but now node is not directly related to a physical feature of the process, see figure 2.
Figure 2. Gate length/node versus node.
ASML has published some very interesting work correlating contacted poly half-pitch multiplied by minimum metal half-pitch to node. For several reasons, I decided to apply the ASML technique to my own data set and determine my own relationship. My reasoning is because ASML:
- Utilized customer data in their analysis they can't publicly share and I can't review.
- The analysis is from 130nm to 3nm and includes several forecast data points.
- It is in half-pitch and I typically work in pitch.
I was able to put together a data set of 54 processes from 12 companies spanning 130nm to 7nm. I do have two forecast data-points at 7nm. The overall fit is excellent with a 0.9911 R2 value. The resulting graph is shown in figure 3.
Figure 3. Standard node versus CPP x MMP.
A couple of notes on this graph. It is update form the one I published previously on SemiWiki with a corrected data point. Also when comparing results calculated with this analysis they are similar to the results from ASML's work.
I then presented a review of lithography limits and the 16nm/14nm, 10nm and 7nm nodes. I have recently reviewed this same material on SemiWiki and I won't repeat it here but refer interested readers to that article available here:
Beyond 7nm there are several challenges to continuing to scale.
Contacted poly pitch (CPP) is made up of the gate length + the contact width and contact to gate space multiplied by two. Figure 4 illustrates the buildup of CPP.
Figure 4. CPP build up.
Each of the three areas that make up CPP have their own scaling challenge.
Studies of mobility versus fin width show a collapse of mobility below a fin width of approximately 5nm. Using 5nm as a limit, minimum gate lengths for FinFETs and horizontal nanowires of ~16nm and ~13nm respectively may be calculated . Scaling contact width increases contact resistance. Scaling down the gate to contact spacing increases the parasitic capacitance. By the 7nm node 85% of the parasitic capacitance for a FinFET will be due to the spacer  necessitating low-k or air gap spacers. A 10-15% reduction is parasitic capacitance at 10nm with air gap spacers was recently shown .
An area of intense research for continued scaling is the implementation of high mobility channels. The use of a Strain Relaxed Buffer (SRB) at 7nm was shown at IEDM in 2016 . Figure 5 illustrates the basic principle that can produce both strained NMOS and PMOS devices. What isn't currently known is whether this was more of a research device or whether this represents what the paper co-authors such as GLOBALFOUNDRIES and Samsung will implement at 7nm. My opinion is we won't see this at 7nm but we won't know until the processes come out.
Long term there are different opinions on the viability of high mobility channels. Figure 6 illustrates some results from a Synopsys simulation that show high mobility channels losing their advantages over silicon by the 5nm node .
Figure 6. Synopsys high mobility channel simulation results.
Issues with CPP scaling put more pressure on MMP scaling to achieve density improvements. The problem with this is scaling down MMP raises interconnect resistance. Furthermore, the lowest metal levels interconnect length is related to CPP and larger CPP values increase interconnect resistance. Even with barrier-less interconnects like cobalt and ruthenium interconnect resistance will be a serious challenge based on our latest projections for CPP and MMP. Figure 7 illustrates a projection of interconnect resistance based on our projections of possible foundry process and at 5nm and below interconnects resistance is a big challenge.
Figure 7. Interconnect resistance challenge.
Based on our current understanding of the 7nm node at the foundries we believe the CPP values are relaxed enough compared to classic scaling that a 5nm node with FinFETs is possible. Using a FinFET gate length limit of 16nm we see a 45nm CPP as achievable and combining that with the 1D EUV metal limit of 26nm would give good scaling.
Beyond 5nm we expect to see a transition to stacked horizontal nanowires (HNW). HNW provides an extra 3nm of gate length scaling and with what we believe to be achievable contact and spacer width values give a reasonable CPP value of 37nm. Combining that with a MMP limit of 20nm achieved with SAQP provides further scaling and is a possible basis for a 3.5nm node.
Beyond 3.5nm we expect another transition to stacking n and p HNW in the CFET concept. This provides scaling without further lithography shrinks. I have seen simulations of a 2-deck process (n over p nanowires) done using Coventor software that show a complete process integration scheme that could provide a 2.5nm node solution. Beyond 2.5nm it may be possible to create a 4 deck CFET solution although integration is very challenging.
Table 1 summarizes a possible scaling roadmap:
Table 1. Foundry roadmap.
I finished the talk with a cost trend projection for a large Taiwan foundry running these processes, see figure 8.
Figure 8. Relative cost per cell trend.
Figure 8 was created using the IC Knowledge - Strategic Cost Model for a greenfield fab in Taiwan with 40,000 wafers per month capacity running each process.
Figure 8, shows a pause in cost reductions from 20nm to 16nm driven by the decision to implement FinFETs at 16nm with no shrink. beyond the 16nm cost reductions resume at the historical rate.
I challenged the audience with this plot, the day before two presenters talked about Moore's law being dead and one presenter specifically mentioned transistor cost going up since 28nm. But I pointed out this plot is very similar to a plot Intel shows in their investor presentations, in fact Intel's cost reduction trend exactly overlays this plot through the 7nm node that is the last node they project. Also at ISS Gary Patton of GLOBALFOUNDRIES discussed a 14nm to 7nm cost per transistor reduction GLOBALFOUDNRIES is achieving.
In conclusion I believe there is a path for continued scaling of density, performance and cost for logic processes into the mid 2020s and beyond with scaling of FinFETs to 5nm followed by HNW and CFETs with multiple decks. Furthermore I believe that cost reductions in line with Moore's law are still occurring and data from Intel, GLOBALFOUNDRIES and other foundries all support this.
 J.P. Colinge, p313, SISPAD (2014).
 Yamashita, et.al. VLSIT (2015).
 K. Cheng, et.al. IEDM (2016).
 R. Xie, et.al. IEDM (2016).