PCIe IP, back in 2004, was my first contact with this amazing world of IP, at least the first on this side of the game, the IP vendor side. I was lucky in that sense that, if I had to learn about this serial, dual-simplex differential protocol, it was also new for the rest of the industry! That makes now more than 12 years that PCI Express is used in the semiconductor industry. If the protocol has been initially defined to be used inside a PC (to replace PCI-X and PCI) or a workstation, the adoption in other industry segments like test equipment or embedded has gone fast.
In fact, in 2017, PCIe is prevalent in designs for storage and cloud computing, but also in mobile and automotive. In the meantime, the specification has moved from 2.5 GT/s for PCIe 1.0 to 16 GT/s for PCIe 4.0 (draft 0.7 has been released in November 2016). Even if the word “draft” may be scary, it’s important to notice that Draft 0.7 is a complete draft and that no functional change is allowed anymore. Moreover, electrical specifications have been validated via test silicon, and two independents implementation were provided to PCI-SIG workgroup members, one from Synopsys, and the other from Mellanox.
The evolution from PCIe 8GT/s signaling to 16GT/s is similar to that of PCIe 2.5GT/s to 5GT/s– primarily a new speed, negotiated at link initialization. Which is new is that getting to PCIe 16GT/s data rates requires a two-stage process. First, the link is brought up to 8GT/s using the familiar 4-phase equalization process, then the same 4-phase process is repeated while running 8GT/s rate to switch to 16GT/s rate.
According with Richard Solomon, Vice-President of the PCI-SIG and Technical Marketing Manager for Synopsys’ DesignWare PCI Express Controller IP, the most significant item introduced by the 0.7 draft is “Lane Margining at the Receiver.” This new feature deserves some explanation, as it uses software to evaluate how close a given lane is to failing to transfer data reliably. The host software can instruct each receiver in a PCIe channel to move its sampling point in time (and optionally voltage) to determine roughly how wide (and optionally how high) the signal eye is at the receiver. The feature can then be used as a system diagnostic/evaluation tool to provide an approximate measurement of the PCIe channel. As you can guess, implementing this feature in a SoC requires close cooperation between a PCIe 4.0 16GT/s controller and 16GT/s PHY.
Implementing such kind of pre-failure system diagnostic looks pretty clever, and good for improving the overall system mean-time-between-failure (MTBF). No doubt that “Lane Margining at the Receiver” will be welcomed in data center, or in automotive (when PCIe 4.0 will be implemented in car electronic, maybe not so soon?), both segments being very demanding for always higher reliability.
The Physical Interface for PCI Express (PIPE) is critical for those designers procuring their PCIe 4.0 16GT/s PHYs and controllers from different sources, as it was already the case, back in 2004, when I was marketing the PCIe 1.0 controller IP. The PIPE 4.4 has been incorporated into the specification by Intel, and the new PCIe 4.0 16GT/s rate is supported using 32-bit, 16-bit, or 8-bit per-lane datapath options. The designers will be dealing with clock rates topping out at 500MHz using 32-bits per lane, all the way up to a staggering 2GHz using 8-bits per lane!
Using a mechanism originally proposed by Synopsys engineers, the PIPE specification now uses a generic register-type interface to provide control and communication between PHY and controller. This mechanism was defined because of the Lane Margining feature, which would have required a large number of new signals in each direction to exchange the needed control and status information between a PCIe 4.0 16GT/s PHY and controller. It can be noticed that this interface could greatly simplify numerous PHY features in the future – both existing ones such as L1 Sub-states control, and potential future controls for higher data rates, more complex equalization schemes, etc.
Do you feel ready for PCIe 4.0 and the 256 GT/s (in 16 lanes configuration), or do you need slightly more information?
You can find the complete article from Richard Solomon: “PCI Express 4.0 Draft 0.7 & PIPE 4.4 Specifications - What Do They Mean to Designers?” here:
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By Eric Esteve from IPnest