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  • Analog, Low-power Optimization at SMIC

    Talking with actual IC designers is always fascinating to me, because these engineers are the unsung heroes that enable our modern day world of consumer and industrial electronics. Too often we only hear from the CEO or other C-level executives in the press about their own companies, products, services and vision. I recently had the pleasure to interact with Josh Yang, Director of the SMIC IP R&D Center about one specific IP block that his group was responsible for designing.

    Q: Which analog IP block did your group design and optimize?

    We recently finished silicon measurements of an ultra low power reference voltage design for IoT application using MunEDA's circuit optimization software. The bandgap reference circuit that we used is a standard topology.

    Article: DAC: It's the Last Week for Many Submissions-bandgap-reference-min-jpg

    Related blog - Three Steps for Custom IC Design Migration and Optimization

    Q: What kind or process node are you designing with and what tools help you to optimize?

    We developed the schematic in our 55nm PDK and used MunEDA's variation aware optimization tools to reduce power consumption, improve output voltage stability, and center the design for the process technology to get a high yield. The used bandgap structure is a conventional general purpose bandgap design for high PSRR and quick transient response. We chose this structure and tuned it manually first, using only SPICE simulation and variation analysis tools, to achieve a low current consumption of 0.5 uA. For the final optimization, we had MunEDA WiCkeD's optimization tools reduce the power consumption by another 40% down to 0.3 uA.

    Q: What are some of the engineering challenges that your analog IC designers faced with this IP block?

    In analog low power designs, more MOS devices will operate closer to their weak inversion region and may become more sensitive to process variation and mismatch. Variation effects must be taken into account when optimizing analog circuits for low power, in order to find a design solution that meets all goals: low power consumption, good performance, and high parametric yield. We found manual design with SPICE simulation and variation analysis tools alone sufficient to find average design solutions, but particularly in the field of low power analog design, the conventional design style leaves a lot on the table. With MunEDA's tools for multi-objective constrained parametric yield optimization we found significantly better solutions when minimizing power consumption with constraints on performance and yield.

    Related blog - SRAM Optimization for 14nm and 28nm FDSOI

    Q: What kind of simulation results did you achieve on this bandgap reference circuit with an optimized design?

    The simulation results after optimization were very impressive.

    Article: DAC: It's the Last Week for Many Submissions-power-consumption-min-jpg

    Q: What kind of design centering results did you get?

    The yield optimizer centered the design very well in the process window with good safety margins for all specs. The optimizer reduced the variation in temperature compensation and in the average output voltage very well:

    Article: DAC: It's the Last Week for Many Submissions-design-centering-min-jpg
    Article: DAC: It's the Last Week for Many Submissions-vbg-average-min-jpg

    Q: The theoretical improvements from optimization look impressive, so what about the measured silicon results for this bandgap IP block?

    So we were eager to see the silicon measured results, because we knew that an optimizer can only be as good as the circuit models are. We took care to characterize our SPICE models well for analog designers, considering small signal parameters, as well as weak inversion / moderate inversion regions that are important for low power analog design.
    Article: DAC: It's the Last Week for Many Submissions-measured-results-min-jpg

    I can say that silicon results exceeded our expectations and matched simulation results very well. All test wafers passed the design spec with 100% yield. Median measured current consumption of the design optimized by MunEDA WiCkeD was 0.27 uA just as predicted by simulation. This excellent agreement between the simulation and silicon data also confirms the high accuracy of the silicon models in our 55nm PDK, which is key for our customers to achieve similar results in their critical analog design applications.Related blog - Tuning Analog IP for High Yield at SMIC

    Q: Do you recommend using an automated approach for optimizing your analog IP blocks versus a manual tweaking approach to meet design requirements?

    We are convinced now that this is the right way to implement advanced low power analog designs in advanced node technology: create good analog SPICE models, and use a good analog circuit optimizer that can handle variation, performance, and current consumption.

    When I started out designing DRAM circuits at the transistor-level back in 1978 we used manual device tweaking, simulation and iteration to help optimize, and it was a very laborious and error-prone process. The project schedule dictated how much time we could spend in manual optimization, and we never felt like all of the circuit parameters had really been optimized. Today, we have a much different world of choices available for transistor-level circuit designers, because they can use a much more automated approach to optimizing their analog IP blocks, like what SMIC just accomplished in their 55nm bandgap reference circuit. The SMIC experience clearly showed that an automated optimization approach with MunEDA tools produced better results than manual device size tweaking and iterating.