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  • REUSE 2016 is Next Week at the Computer History Museum!

    Article: Silicon-Accurate Mixed-Signal Fractional-N PLL IP Design Paper-computer-history-museum.jpgThe first REUSE Semiconductor IP Tradeshow and Conference is next week at the Computer History Museum in Mountain View, CA. Given the importance of IP I would strongly suggest attending this event. The presentation abstracts are up now and there are a few I want to highlight as they are companies that we work with on SemiWiki:

    HBM2 IP Subsystem Solution for High Bandwidth Memory Applications:
    The most common memory requirements for emerging applications, such as high performance computing, networking, deep learning, virtual reality, gaming, cloud computing and data centers, are high bandwidth and density based on real-time random operations. High Bandwidth Memory (HBM2) meets this requirement and delivers unprecedented bandwidth, power efficiency and small form factor.

    HBM2 (X1024) offers the maximum possible bandwidth of up to 256 GBps compared to 4GBps with DDR3 (X16) at 1/3rd of the power efficiency. HBM2 and 2.5D silicon interposer integration unlock new system architectures, therefore, causing HBM2 ASIC SiP (system-in-package) to gain popularity among OEMs. One of the key IPs used to develop these ASIC SiPs is the HBM IP subsystem that consists of controller, PHY and die2die I/O. Open-Silicon’s HBM2 IP subsystem fully complies with the HBM2 JEDEC® standard.

    The IP translates user requests into HBM command sequences (ACT, Pre-Charge) and handles memory refresh, bank/page management and power management on the interface. The high performance, low latency controller leverages the HBM parallel architecture and protocol efficiency to achieve maximum bandwidth. The IP includes a scalable and optimized PHY and die-to-die I/O needed to drive the interface between the logic-die and the memory die-stack on the 2.5D silicon interposer.

    Open-Silicon’s HBM2 IP subsystem addresses the implementation challenges associated with interoperability, 2.5D design, overall SiP design, packaging, test and manufacturing. Multiple built-in test and diagnostic features, such as probe pads and loop-back for issue-isolation within the various IP subsystem components, not only address the test and debug challenges, but help in yield management and yield improvement, while ramping HBM2 ASIC designs into volume production. Open-Silicon’s HBM2 first implementation solution in TSMC 16nm FF+ features 2Gbps per pin data rate at up to 5mm trace length. This enables a full 8-channel connection from a 16nm SoC to a single HBM2 memory stack at 2Gbps, achieving bandwidths up to 256GB/s.

    2:30pm-3:00pm Boole Room: Dhananjay Wagh , Principal IP Architect & Innovation Manager of Open-Silicon

    A Vibrant 3rd Party IP Ecosystem is Critical to the Growth of the Semiconductor Industry
    The third-party IP ecosystem plays a critical role in the growth of the semiconductor industry. Taher Madraswala, president and CEO of Open-Silicon, will discuss the state of the IP market and how the functional integration of IPs is driving new market applications.

    He will discuss the importance of choosing the right IPs in order to achieve first time silicon success, as well as the benefits of leveraging third-party IP compared to internal IP development. Taher will describe case studies of complex SoCs, completed for leading OEMs, that were highly successful through leveraging the third-party IP ecosystem. Designers are finding new ways to produce less expensive SoCs with 2.5D interposer based system-in-package (SiP) designs, which enable a mix and match of chip/IP components at optimum process nodes.

    This approach will greatly increase the reuse of IP developed at older process nodes. Additionally, as IP integration costs are increasing due to the rising number of discrete IP blocks in the current generation of SoCs, designers are leveraging IP subsystem-based design methodologies to lower development cost and risk. Continued developments in the third-party IP ecosystem, for new trends like 2.5D SiP and IP subsystems, will enable the semiconductor industry to continue to innovate and evolve.

    4:30-5:00pm Hahn Auditorium: Taher Madraswala, President and CEO of Open-Silicon
    And don’t forget I will be giving away signed copies of “Mobile Unleashed” at the cocktail reception from 5pm-7pm. Register for REUSE 2016 for free HERE. You can read more about Open-Silicon on SemiWiki HERE.

    I hope to see you there! By the way, "Mobile Unleashed" currently has a five star rating on Amazon!

    Also read: Bringing the Semiconductor IP Community Together!


    Article: Silicon-Accurate Mixed-Signal Fractional-N PLL IP Design Paper-mobile-unleashed-banner.jpg