You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • SiFive execs share ideas on their RISC-V strategy

    Since its formation just last year, SiFive has been riding the RISC-V rocket from purely academic interest to first commercialization. In an exclusive discussion, I talked with CEO Stefan Dyckerhoff and VP of Product and Business Development Jack Kang about their progress so far and what may be coming next.

    Article: A Brief History of RTL Design-sifive-dyckerhoff-kang.jpg

    Previously, I covered the introduction of the SiFive Freedom E300 and U500 platforms of RISC-V IP cores. From the comments we got, I’m not sure people understood what the SiFive business model is, or what their ecosystem looks like. As Dyckerhoff put it, SiFive is at the tail end of its design process with its initial offering commercial cores – but there is a lot more to the strategy.

    “We help solve compute problems benefitting from customization,” Dyckerhoff said. RISC-V is an open source instruction set giving implementers complete freedom to create silicon solutions. SiFive provides RISC-V expertise in two basic go-to-market strategies: selling IP, including support and customization; and complete turnkey system-centric chip projects. Dyckerhoff represents Sutter Hill Ventures and comes from Juniper Networks, and was also deeply involved with P.A. Semi prior to the Apple acquisition, and he gets this OEM-enablement model.

    The first success story for SiFive was supporting Microsemi in a 2-month project for one of their end customers, delivering a customized E300 core in an FPGA. (My guess at who that customer might be – starts with an A, ends with ‘us’ – was unconfirmed. The cone of silence is working properly.) The Freedom E300 SF2+ FPGA Dev Kit available on the SiFive developer site is a by-product of that effort. It’s always good to have that satisfied lead customer in the bag. That has helped SiFive to grow to employee #18 so far.

    Speed is the essence of this model. The tricky part of engagements is to find a way to translate a moderate up-front investment into medium revenue quickly at low risk. If there were huge revenue on the table, an OEM could choose to do an SoC themselves, but it’s a big leap. Even medium-sized projects can siphon off a lot of resources if teams aren’t careful, especially when it comes to custom silicon. “We want to radically drive down human involvement in design costs,” says Dyckerhoff. He says processor IP today is overvalued, while the hard part is implementing the SoC – and 80% of the stuff in that SoC doesn’t add value to the actual application.

    Those are intriguing comments, given developments in September. One of the companies to jump on the RISC-V bandwagon is UltraSoC, with their universal SoC debug solution. Also on board is Fedora, releasing a complete RPM-built bootable disk image of Linux. Kang says the lead implementer for KVM has also reached out with questions, and there is the Apache MyNewt project for a deeply embedded RTOS.

    Although SiFive isn’t targeting ARM specifically, Dyckerhoff says there was a definite uptick in developer registration activity after the SoftBank acquisition of ARM. I asked about what application segments they are seeing activity in – for instance, my barking chain says SSD providers are very interested since the flash controllers are heavily customized. Again, no specific confirmation, but it does fit the profile. Both Dyckerhoff and Kang commented that they are hoping to catch people heading from “classic MCU to IoT-ish” projects needing more customized silicon, something I’ve been saying is happening for a while.

    There’s also a very big development on the horizon. One of ARM’s turning points was introduction of AMBA. Its motives were self-serving – to get chips designed faster, it had to be easy to connect in the processor IP, so they firmed up a specification. It ultimately had the opposite effect; as more ARM processor IP was fielded, other IP providers had to adopt AMBA if they hoped to get designed in.

    In the RISC-V community, TileLink could provide that same type of turning point. It’s the cache coherent interconnect layer, and it does bridge into AXI4 via the NASTI interface. SiFive teams have stepped in to help edit the TileLink specification and formalize it for public consumption, and although the timeframe isn’t firm Dyckerhoff hinted we might be within a couple months of release. That could break loose an entire chain of RISC-V IP offerings.

    I asked SiFive about China in particular. Their response was a bit surprising: it’s not currently a high-priority focus. Dyckerhoff has a lot of experience competing in China from his Juniper days (read: Huawei), and understands what would have to happen to succeed there. He did say with SoftBank in the picture as a Japanese firm, there have been rumblings about cultural rivalries, but nothing earth-shattering in the works yet. Possibly sandbagging, but given their size and ample opportunities I believe this.

    The last comment may have been the most interesting. Dyckerhoff says yes, SiFive is for-profit, created to solve immediate business problems. He sees their mission as doing that in the most “extremely friendly to open source” way possible. I take that to mean that while they aren’t necessarily giving away all their RTL (not a requirement of the RISC-V Foundation, BTW), they are committed to get to open source interface specifications created and to have open source software ported. For instance, SiFive teams are maintaining the current "Rocket" open source core implementation.

    There are a ton of parallels between the early days of ARM and where SiFive is headed. ARM was at a headcount of 70 in 1994 when they hired Warren East to run their consulting operation, where ARM engineers co-designed chips with customers. AMBA debuted in 1997 after the stunning success of ARM7TDMI. SiFive doesn’t have critical mass of high-profile design wins just yet, but is laying the necessary groundwork to reign in academic thinking around RISC-V.

    The progress SiFive has made so far is substantial; granted they are bootstrapped on a couple years of predating RISC-V efforts. I do think there is more customer activity going on than people are willing to talk about. When the TileLink spec is published, that should free up critical resources for driving new customer engagements. I’d also look for what other open source software comes into the fold for hints on how application segments will develop.