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  • Up front phases improve CDC analysis

    Many tools find clock domain crossings (CDCs) in FPGA designs. Some donít find the right ones since they donít comprehend things like in-house synchronizer constructs. Some find too many based on misunderstanding intent, inaccurate constraints, and other factors that lead to noise. A new Aldec webinar offers guidance to improve CDC results.

    Sergei Zaychenko of Aldec offers one diagram as a refresher on how CDCs create metastability, and the variables that factor into MTBF. His ďimpossible to avoidĒ comment Ė if there are multiple clock domains, there are CDCs by definition Ė suggests the urgency of finding and mitigating CDCs in an FPGA design.

    IO Design-cdcs-mtbf.jpg

    Zaychenko of course uses Aldec ALINT-PRO to illustrate the concepts of CDC detection, using a phase-based methodology. As the name implies, ALINT-PRO is a linting tool, using a set of rules to check constructs against. Users enter their FPGA design normally, then use ALINT-PRO to run through clocks, resets, I/O, and structural CDCs. This produces a report of critical rule violations and a quality percentage.

    Itís interesting that Aldec sets the minimum pass percentage at 70%; that figure is configurable. This factors into the noise problem posed in the opening. Zaychenko says in many cases, after critical violations are flagged, what remains are items that might be waived once identified. He cites examples of unspecified clock relations versus automatic clock signal recognition that might generate false CDCs.

    IO Design-aldec-alint-pro-cdc-flow-manager.jpg

    On the other hand, there might be some serious problems that need attention. An example is a clock interacting with a ďblack boxĒ. The clock tree might be incomplete, and there may be CDC issues lurking. ALINT-PRO puts black box pins into a special unclocked domain. The user may enter block-level constraints to further describe the intent of the black box and resolve the flagged items.

    Zaychenko continues describing a few common clock-related CDC issues, and similar issues with reset signals. Itís clear from the discussion that the out-of-box Aldec linting design rule set in ALINT-PRO, developed and enhanced with ongoing customer feedback, is quite robust. He also shows how the clock and reset issues are presented in a viewer with cross-probing to the RTL schematic. There are also abstracted schematic views of clock and reset circuits.

    IO Design-cross-probing-aldec-alint-pro-cdc.jpg

    After a similar discussion on I/O delays and checking, the design is ready for the structural CDC checking phase. This looks at CDCs and synchronizer constructs. Why doesnít ALINT-PRO just jump right to this phase? Zaychenko says that if the clock, reset, and I/O phases are clean, there is an observed 10x reduction in CDC noise at the structural check phase. Keep in mind that much of that reduction is users helping themselves with better constraints. However, the automated guidance provided by ALINT-PRO speeds the process of finding missed or badly defined constraints much more quickly and thoroughly than a manual review of a large design.

    Aldecís approach to CDCs goes one step farther: a functional CDC testbench, modifying the original testbench with additional assertions and coverage statements, and added metastability insertions. (That is another entire webinar session found in Aldecís archives.)

    To demonstrate the entire flow, a simple multi-clock reference design is included with ALINT-PRO. Without constraints, it presents over 100 false crossings. Applying the phase-based approach wipes out critical errors, uncovers an undetected CDC, and reduces the false crossings to nil. While a simplified example, it does show what this flow can do.

    To view this recorded webinar in entirety (one-time Aldec registration):

    Efficient CDC Debugging Using Phase-based Methodology for Large FPGA/ASIC Multi-clock Designs

    This webinar is aimed at two types of designers: those not using a CDC checker, and those using a CDC checker other than Aldec. I canít help but think a CDC tool that jumps straight into structural checking is missing problems, presenting false issues, and just not giving an accurate picture that takes too long for design teams to sort out. That may be giving all CDC tools a bad rap. Iíd encourage those who think CDC tools arenít effective to give this event a view.