You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • Intel Stratix 10 MX FPGA Highlights

    Article: Over-under: Apple, 52M iPhones in 4Q-stratix_mx10.jpgThese days, FPGAs are fairly complex pieces of silicon. Being that the case, it would take several articles even to put a summary of the features embedded in high-end FPGA devices. Hence, in this article, I will concentrate in just one feature, namely, the new embedded memory blocks of the recently released Intel-Altera Stratix 10(1).

    Even medium sized FPGAs include quite a big quantity of memory blocks. For example, Altera's Cyclone V family includes memory blocks in the range of 1.4 to 12.2 Mbits (2). These memory blocks are not concentrated in a single spot but distributed over all the FPGA silicon, to reduce routing complexity when connecting the memories to the FPGA logic blocks. These memory blocks find plenty of uses: buffers, FIFOs, filters, fast memory/cache for embedded processors, register banks, etc.

    As useful as these banks are, they are light-years away, size-related, compared to today's DDR memory banks. Well, this has changed completely with the release of Stratix 10 MX, since these devices embed DDR memory banks. Intel's acquisition of Altera has had many consequences, one of them being the merging of technologies from both firms. The Stratix 10 MX includes Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology, to interconnect between the FPGA fabric and the DDR memory blocks.

    The DDR memory blocks used on the FPGA are 3D stacked blocks, integrating high speed data channels, dubbed HMB2 - High Memory Bandwidth. The HMB2 3D memory is connected to the FPGA core through parallel channels. Each channel can provide a bandwidth of 16Gbps, multiplied by 16 channels, give a total bandwidth of 256Gbps.

    Moreover, the memory is separated in up to 4 "tiles", each one connected with its own 16 data channels. The total bandwith for four tiles is of 1Tbps. Compare this number with current BW from a DDR1600 memory bank, which is in the order of 100Gbps, or even DDR2133, which provides around 140Gbps.

    Currently available Stratix devices have embedded memory banks ranging from 4 to 16 GByte. In case you were wondering, these new memories do not replace the aforementioned static memory banks. Stratix MX 10 devices have between 86 to 127 Mbit in static memory blocks.

    Other advantages of the integrated memory blocks, compared to current distributed solutions (3), include lower power consumption and reduction of the real estate on board, as well as a reduction in PCB interconnection complexity.

    The availability of these new devices promises to change the architecture for solutions that are currently dominated by CPUs and/or GPUs, like database management, cyber security, genetic algorithms and deep machine learning. For an example regarding this last category, please refer to my article: FPGAs and Deep Machine Learning

    My blog: FPGA Site

    References:
    Stratix 10 MX Devices Solve the Memory Bandwidth Challenge
    Altera's 3D System-in-Package Technology
    Stratix 10 MX Product Overview Table

    Image Source:
    Stratix MX10 blocks - Intel/Altera

    Notes:
    (1) - Altera and Xilinx are the major players on the FPGA arena. Last year (2015) Altera was acquired by Intel.
    (2) - These numbers can be increased a bit more, around 15%, by converting some of the ALM logic blocks onto memory blocks.
    (3) - A typical distributed solution is based on separated CPU, FPGA and memory SODIMM cards, compared to the Stratix MX10 solution that includes CPU (ARM Cortex), FPGA, and memory on a single package.