On September 28th TSMC and Solido are teaming up to share what they have learned about dealing with variation in advanced process nodes. They are hosting a webinar where they will talk about variation in memory and standard cells designs. The focus of the webinar will be on how TSMC uses Solido’s new Variation Designer 4.
Jacob Ou from TSMC will be speaking. He is a technical manager at TSMC with extensive experience in simulators, PDK’s, routing, and supporting customer designs. Solido’s Kristopher Breen we’ll also be speaking. He is vice president of customer applications at Solido Design and also has extensive experience in the development, deployment and support of variation aware design and verification solutions.
The components of a memory design need to be verified at High Sigma. Without adequate verification methods designers often resort to adding redundancy, increasing supply voltages or running at lower clock rates. All of these potential solutions have high costs and can affect a product’s success in the marketplace. Solido’s Variation Designer 4 Includes several powerful proven technologies for solving these problems. One is their High Sigma Monte Carlo the other is their Hierarchical Monte Carlo. Better verification leads to more competitive memory products.
Conventional methods of standard cell verification for cell delays and transition times are simply impractical from a compute resource and tool license perspective. Yet standard cells need to be carefully analyzed because the effects caused by variation do not manifest in a classical Gaussian curve. In fact, they have extremely long tails which makes adding arbitrary amounts of margin ineffective as a definitive way to guarantee chip performance. Once again High Sigma is required to ensure a high success rate. Solido has two technologies for helping out with standard cell verification. Fast Monte Carlo can be used on large batches of standard cells out to three Sigma quickly and reliably. Then High Sigma Monte Carlo can be used for accelerating High Sigma verification so that it is feasible for standard cell libraries.
One of Solido’s advantages is its extensive experience with variation in semiconductor designs. It should be very interesting to see what Jacob and Kristopher have to say about their experiences in these two areas. The webinar will be held on September 28 at two different times. It will be available at 10 AM Pacific Time and also at 10 AM in China Time Zone. This webinar should be interesting for IC designers, design managers, cad managers, as well as design directors.
Here is the link for registering for this webinar on the Solido website.