WP_Term Object
(
    [term_id] => 24
    [name] => TSMC
    [slug] => tsmc
    [term_group] => 0
    [term_taxonomy_id] => 24
    [taxonomy] => category
    [description] => 
    [parent] => 158
    [count] => 560
    [filter] => raw
    [cat_ID] => 24
    [category_count] => 560
    [category_description] => 
    [cat_name] => TSMC
    [category_nicename] => tsmc
    [category_parent] => 158
)
            
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WP_Term Object
(
    [term_id] => 24
    [name] => TSMC
    [slug] => tsmc
    [term_group] => 0
    [term_taxonomy_id] => 24
    [taxonomy] => category
    [description] => 
    [parent] => 158
    [count] => 560
    [filter] => raw
    [cat_ID] => 24
    [category_count] => 560
    [category_description] => 
    [cat_name] => TSMC
    [category_nicename] => tsmc
    [category_parent] => 158
)

NVIDIA looks inside Parker and automotive-grade

NVIDIA looks inside Parker and automotive-grade
by Don Dingee on 09-07-2016 at 4:00 pm

‘Parker’ is a fascinating name for a chip designed for autonomous vehicles – more likely, the project name was pulled off a map as a bedroom community near Denver. First highlighted on the roadmap in 2013, and advertised as inside the DRIVE PX 2 platform shown at CES 2016, NVIDIA revealed some details of Parker at Hot Chips 2016.


That slide is noteworthy because of what changed between then and now. After previewing this version of the roadmap a little over three years ago, NVIDIA elected to jump into a modified tick-tock cadence, perhaps a nod to the risk in getting an advanced architecture on an advanced node. The 64-bit homegrown ARMv8-A Denver core first appeared in the 28nm Tegra K1, and for the Tegra X1 in 2015 on TSMC 20nm NVIDIA fell back to the ARM Cortex-A53 as the big core.

In Parker, a second-generation version of Denver appears on TSMC 16FF, paired with four Cortex-A57 cores on the LITTLE side. NVIDIA clearly firmed up big.LITTLE support for Denver 2 and indicates they also tweaked code fetch and power retention states, and updated the cache coherent interconnect fabric. NVIDIA insists on showing benchmarks versus other mobile SoCs, touting a near 40% increase over the Apple A9X – even though the tablet wars have long since cooled off.


Deep learning and automotive is now where the action is. The longer timeline of the Denver 2 effort allowed GPU technology to move forward, and the latest Pascal GPU with a whopping 256 core complex is on chip. This gives Parker some 1.5 teraflops of compute power for “cockpit systems”. That’s an indication of where NVIDIA wants to go, combining graphics power for display with compute power for automotive sensor fusion tasks to provide a complete experience inside the next-generation car.

That got me wondering: how is NVIDIA taking mobile class stuff and hardening it for the automotive environment? It’s one thing to say parts are good for automotive. There are three parts to making good on that story.

The first one is relatively easy: integration. Not shown on the Parker block diagram is a dual-CAN interface, allowing Parker to talk to common automotive peripherals. Also, Gigabit Ethernet is gaining momentum in vehicles, with IEEE 802.3bp more commonly known as 1000BASE-T1 completed a couple months ago. This is the uptick of the one pair Ethernet approach to reduce cabling and improve EMC for cars. GigE goes hand in hand with 4K video capability for bigger cameras and more robust displays.

Another step is ISO 26262 compliance, which NVIDIA claims to have achieved with Parker. In the lower left hand corner is a “safety engine”. NVIDIA didn’t give a lot of detail there, other than saying they have a dedicated dual lockstep processor – presumably with two ARM Cortex-R cores, although not disclosed – which handles fault detection and processing. There also must be some enhancements in the SoC interconnect, although no word whose technology they are using. The DRIVE PX 2 is termed a Safety Element out of Context (SEooC) in ISO 26262 lingo.

The most interesting thing is how NVIDIA is getting to automotive environmental specs with TSMC 16FF. In a word, it’s screening. NVIDIA claims support from -40 to +105 C, along with complete ISO 26262 compliance. They are binning processors after a 24-hour burn-in, and doing further testing to determine what they call “unit level drift” and tossing more parts that look like they may have long-term reliability problems. Expensive, but pretty much the only way to get to an acceptable level of reliability for complex SoCs at temperature extremes.

A bit more on the chip, including the support for hardware virtualization, is in NVIDIA’s blog on Parker. How NVIDIA completes this pivot from mobile to automotive, and how other SoC makers respond, will be something to watch. We’ve seen several vendors slap the automotive label on SoC without really explaining the ISO 26262 and environmental approach; what they really mean is infotainment-ready. NVIDIA clearly isn’t satisfied there, and may have a head start, but I’d expect other vendors to follow with similar steps shortly as the stakes are getting higher.

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