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  • Flex Logix validating EFLX on TSMC 40ULP

    Flex Logix has been heads-down for the last several months working toward customer implementations of their EFLX reconfigurable RTL IP cores. Today, they’ve announced a family of 10 hard IP cores ready in TSMC 40ULP, and provided an update to their roadmap for us.

    CEO Geoff Tate emphasized that as a small company with a substantial investment in qualifying IP against stringent TSMC processes, Flex Logix is very customer-driven in prioritizing their projects. It’s very interesting they chose the smaller EFLX-100 core to go first in 40nm, and Tate indicates that is a function of MCU and IoT demand from lead customers.

    IP-SOC 2012 Call for Papers!-flex-logix-eflx-roadmap-jpg

    As you may recall, the EFLX tiles can be grouped into arrays up to 5x5, providing up to 3000 LUTs. There are also two flavors of EFLX tile, one more general-purpose logic at 120 LUTs and one more DSP-oriented, with 88 LUTs and 2 MACs with 22x22 multipliers. In TSMC 40ULP, these both check in at 0.13mm2, requiring only 5 metal layers.

    Getting from two basic family members to 10 variants in the family is an illustration in just how much work is involved. Tate says that the basics of tile interconnect can be completely proven in a 2x2 array, but checking performance and power requires a bit more creativity. “Customers tend to care more about power at 40nm,” he said, and Flex Logix has to fit into what a customer has selected for threshold voltages.

    At TSMC, that includes low Vt (LVt), standard Vt (SVt), high Vt (HVt), and extra-high Vt (eHVt). eHVt is popular for configuration bits that don’t switch after being programmed. SVt is needed to get performance out of switching logic. That leads to design of a TSMC validation chip with several permutations of EFLX-100 arrays in various threshold voltages.

    IP-SOC 2012 Call for Papers!-flex-logix-eflx-validation-chip-tsmc-40ulp-jpg

    The validation chip also has blocks of SRAM used to test each array at-speed with vectors for performance and power characterization. Patterns are run from one SRAM block and results are caught on another. There is also a Vdd monitor – as with any programmable logic, the exact voltages applied to the transistors are important. To make sure there are no ill effects from static and dynamic IR drop, the voltage is monitored precisely at each EFLX array during testing, across the combinations of threshold voltages and across the operating temperature range.

    With the EFLX-100 in fabrication, Tate expects fully validated silicon in 4Q16. Their initial results are quite good – they have used a True Circuits PLL and are getting speeds of 300 MHz. They have also measured state retention down to 0.5V (remember, these are SRAM-based programmable logic arrays). Once completely characterized, a full validation report on TSMC 40ULP will be available under NDA; reports for TSMC 28HPM/C are already available.

    The press release has a few more facts and figures:
    Flex Logix Reconfigurable, Low-Power IP Cores Now Available for TSMC 40ULP

    I also asked Tate about the progress on TSMC 16FF. He says his teams are working through a few nuances of the process and tweaking transistors in EFLX accordingly, and things are going roughly as expected. Before they announce readiness they have to get to a similar point at TSMC with a validation chip and initial testing and a lead customer ready for the IP.

    The progress at Flex Logix has been quite good in just over two years since formation. Qualification at TSMC is non-trivial, and having IP fully characterized is essential for customers to be able to pick it up and design it in without issues. TSMC 40ULP brings in a much larger pool of design starts that can take advantage of point reconfigurability in an SoC.