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  • Statistical Simulation Provides Insight into 6T SRAM Optimization

    ARM’s Azeez Bhavnagarwala recently gave a talk hosted by Solido on the benefits of variation aware design in optimizing 6T bit cells. Azeez sees higher clock rates, increasing usage of SRAM per processor and the escalating number of processors, shown in the diagram below, as trends that push designers toward 6T. Six Transistor (6T) bit cells are preferred for SOC applications because of their small area and relatively low power requirements. He sees increased demand for larger and lower cost L2+L3 cache is creating never ending pressure to reduce power and area without compromising performance.

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    For IoT there are competing needs though that cause contention in selecting between 6T on one hand, or 8T and 10T on the other. Out of the box, 8T and 10T have lower active Vmin’s than conventional 6T cells. So despite the area penalty they sometimes win out. Azeez points out in his talk that there still are excellent reasons to employ 6T bit cells. First off, they are heavily optimized by the foundry during process development. With this comes readily available design and verification flows. Finally, as mentioned above, they are going to save area and power.

    Let’s take a look at the three primary challenges for SRAM designers in Azeez’s view. Vmin’s need to be ultra-low, near threshold – below 400mV. This comes about from IoT device operation expectations for up to days, weeks or months between charges. At the same time some of these IoT devices need to operate in the gigahertz range to deliver the proper level of user experience. Rounding out the challenges is the need for retention Vmin that disp into the sub-threshold region. It’s not uncommon to see these low voltages combined with specs calling for only 100’s of femto amps per bit for retention in order to deliver battery sipping performance.

    So how can designers respond to improve 6T Vmin? The foremost answer to this question is to include “write assist” in the design. Write assist helps the bit cell by further weakening the PFET and strengthening the NFET for the duration of the write operation. There are a vast number of circuit design techniques used to accomplish this, but one of them stands out once statistical analysis is brought to bear on the problem.

    I have written recently about how Solido’s software can be used to ensure high yield in the face of variation. Interestingly variation aware analysis can also be used to find optimal operating points in cases like this where we are seeking the best write behavior and the lowest circuit Vmin. To implement write assist the main choices are: lower Vgs on the PFET, higher Vgs on the NFET or on the NFET Vds. Methods to do this include raising the virtual ground with a negative bit line, or lowering the column VDD or the WLOD.

    Azeez’s work shows that lowering the column VDD is most effective. His use of Solido for statistical simulations shows dramatic results. This approach gives the largest improvement in decreased write voltage – it enables near VT write operations in a variety of 6T configurations.

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    However, even more interestingly, it tightens the distributions for write voltages as the voltage is decreased. This is an unusual win-win for the circuit designer who is usually faced with an unpleasant trade off choice. Here, lower voltages come with improved write performance. Other write assist methods do not come with the benefit of variation immunity to device fluctuations.

    Azeez shows that even the alternative of going from planar to FinFET will not produce as large a benefit. Statistical variation aware analysis shows a method to achieve higher process performance through circuit design techniques than can be obtained by a process technology switch. In his talk Azeez also points out other optimization that can be applied by using statistical analysis for other aspects of the memory design. To see the entire talk, you can look here on the Solido website.