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  • Are Your Transistor Models Good Enough?

    SoC designers can now capture their design ideas with high-level languages like C and SystemC, then synthesize those abstractions down into RTL code or gates, however in the end the physical IC is implemented using cell libraries made up of transistors. Circuit designers use simulation tools like SPICE on these transistor-level netlists to ensure that the specifications for timing, power and standby current are being met across process, voltage and temperature (PVT) corners to account for process variation effects. This all begs the bigger question, "Are your transistor models good enough?" If your transistor models are not quite accurate enough, then the SPICE simulation results will give you inaccurate numbers and your next chip may fail to be competitive or simply not work at all.

    Fortunately we have an EDA industry where such critical questions about transistor models are being addressed. There are four major tasks that should be considered when discussing transistor model accuracy:

    • Device model extraction
    • QA of the models versus silicon
    • Cell circuit validation
    • Design oriented model characterization


    In the past you may have used four separate tools for each task listed, maybe from different vendors or even your own custom scripts. Today it's possible to use a single SPICE modeling platform called MeQLab provided by Platform Design Automation that spans all four tasks.

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    Article: Verifying Finite State Machines-meqlab-min.jpg

    Related blog - A Brief History of Platform Design Automation

    With the MeQLab tool there are five types of engineers that will benefit from using it to get their specific questions answered:

    • Foundry modeling engineers - need to generate new models: device, corner, statistical, mismatch. Circuit level verification also needs to be performed.
    • Foundry model QA engineers - have the task of verifying each SPICE model library then produce a model report for review.
    • Design house foundry engineers - will double check that the foundry SPICE models are ready for use by circuit designers.
    • Circuit design engineers - they need to optimize either the process or a specific IP block to get the right performance for a given process node.
    • Researchers - looking into device-level research topics requiring data analytics, model extraction, QA, or process and device optimization.


    Device model extraction is the mathematical process of measuring silicon wafer characteristics (current, voltage, resistance, capacitance, charge), then creating industry-standard models used for IC devices: MOS, SOI, BJT, Diode, Resistor, Capacitor, Varactor or user-defined circuit. All of the latest FinFET models and BSIM6 are supported, so it fits into your existing EDA tool flow. Wafer Acceptance Test (WAT) data can be viewed graphically or numerically, corner models are automatically generated, Length of Diffusion (LOD) models generated, plus both HSPICE and Spectre models are generated. Here's a screen shot of model parameters fitted to curves based on measurements:

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    Statistical modeling is a popular approach that enables circuit designers to simulate their transistor-level IP to see how it will perform across process variations, although creating accurate statistical models can be quite time-consuming to run on modern CPUs. With the MeQLab approach there is an internal SPICE simulation that produces statistical models 100X faster than with a traditional SPICE tool because Platform DA is using their own machine learning algorithm to get faster simulation speeds to create statistical models and mismatch models.

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    IDlin of NMOS vs. PMOS

    With smaller process nodes we've learned to accept more model corner models to account for new physical effects, so to account for both global and local variations you can start with a 5 corner model library then have an 11 corner model library automatically generated. Have a Quality Assurance (QA) verification process ensures that your models will be free of data issues like:

    • Fitting errors
    • Scalability
    • Crossing data
    • Kinks
    • Out of bounds
    • Not smooth enough


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    Another time-saving feature is the ability to quickly compare two model libraries, let's say looking at an HSPICE model library versus a Spectre model library. Perhaps you have version 1.0 and 1.1 of the same model library and are curious to know exactly what has changed in the model library so that you can better understand the impact to your existing IP blocks.

    A final type of QA that comes with MeQLab is the ability to use your existing PDK (Process Design Kit) files and then automatically run comparison circuits between pre-layout and post-layout simulations using just a few mouse clicks, saving you valuable setup and analysis time from doing a manual comparison.

    If your company designs for high voltage environments like automotive or industrial then it's good to know that MeQLab supports the two most popular models, HiSIM_HV and the proprietary Level 66/101 HV models for use in commercial circuit simulators like HSPICE or Spectre.

    Memory designers for SRAM will save time by using the automation features to view buttery charts, Static Noise Margin (SNM), Write Noise Margin (WNM), plus get a statistical analysis of their SRAM cell performance:

    Article: Verifying Finite State Machines-sram-min.jpg

    If you need to perform noise characterization, then the MeQLab software can be connected to a specialized hardware testing platform called the NC300, giving you noise modeling and statistical/corner noise modeling. For VCO circuits you can even analyze the effects of 1/f noise.

    Design or process optimization is an important technique to make your silicon IP differentiated from competitors, so there's a neat optimizer feature in MeQLab where you can specify a circuit performance as your target then optimize model parameters with circuit or process parameters. Here's a snapshot of optimizing a delay time versus Vsupply across different temperatures:

    Article: Verifying Finite State Machines-optimize-min.jpg

    Bright Power Semiconductor
    Located in Shanghai is a virtual IDM called Bright Power Semiconductor that does AMS IC designs for LED lighting, motor drive products and home appliance products. Here's what they have to say about using MeQLab:

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    “With the unique features above and complete modeling offerings embedded on a single platform, MeQLab were quickly adopted by the industry’s leading foundries, design companies and IDMs, MeQLab not only helps foundries to generate SPICE models faster and with better quality, it also helps design companies to improve margin and better protect circuit IP, Bright Power Semiconductor, world’s leading chip vendor on LED lighting products, has adopted MeQLab for optimizing foundry models and customizing models for its own process, “foundry models address a wide range of applications, so accuracy is balanced between device geometries and bias conditions, for our designers, we always have the need for optimizing foundry models to better suit our design needs, however device modeling has always been a challenging task to us until we adopted MeQLab, it addresses all the modeling needs including circuit validation and with the high voltage device modeling knowledge built-in, the work is getting much easier, also PDA team has provided excellent support and training sessions for our designer to quickly catch up speed with device modeling, we are pleased that we chose MeQLab as our modeling platform”

    Tom Zhang, Director of Process Development

    Summary
    Circuit designers, foundry modeling engineers, model QA engineers, design house foundry interface engineers and researchers can all benefit from using a tool like MeQLab to perform device model extraction, QA, cell circuit validation and design oriented model characterization. Instead of piecing together dissimilar software and scripts, why not use something commercially available that was defined for that purpose.