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  • efabless SemiWiki FAQ

    Article: Intel's Haswell and the Tablet PC Dilemma-efabless-github.jpgThe first post on efabless generated some interesting questions that I will re-post here. Again, crowdsourcing is an iterative process so your help is greatly appreciated:

    Please forgive me my ignorance, but what is the difference between efabless and ChipEstimate?

    At efabless, the customer can search and purchase or license IP, but more importantly the customer can also request derivatives and new IP directly in the efabless marketplace, including IP to be designed by the efabless community. We are in the process of revamping the website with the messaging on what can be done now and what is coming.

    I'm actually a bit confused reading the article! What is meant by the term "IP" here? If "IP" is referring to architectural/u-arch designs, isn't that already being done by players like ARM and Intel? Or is "IP" referring to the synthesis of the u-arch designs into Si, the process which is now open-sourced, unlike the earlier process where you had to talk only to "fabs"? Also, the company's website didn't seem to provide enough information (or maybe I just didn't do a good job of searching deep enough).

    Our reference to “IP” is for analog, digital and mixed-signal functional building blocks used to design a larger, more complex system or subsystem functions within an ASIC or an SoC. The IP functions have historically been developed and provided by companies that have access to the foundries, design SW and customer access.

    The efabless platform provides a medium for the designer community to share IP sources and collaborate in co-creating more complex designs. We provide the connection to the foundries, the legal framework, a complete EDA toolset and a marketplace to enable the community to monetize their design work.

    The website content is being updated to reflect more comprehensive description of the offering and the capabilities. Today the platform supports, analog schematic design and simulation, full digital design RTL-to-GDS in September, and chip assembly and analog layout and physical verification LVS/DRC thereafter.

    Couple of questions come to mind (and some comments):

    1. Alberto Sangiovanni (a very famous semiconductor expert) spoke about the platform-based design methodology of h/w in the early 2000s, where he emphasized that h/w components can be picked off-the-shelf and integrated to form a system. This naturally requires a library of components. The approach so far has been that semicon companies compete to use their own components (only using off-the-shelf IP for major pieces like the CPU, and only for low-cost products). Although adopting crowd-sourcing would stop this competition (and enable smaller companies to build their own h/w), how easy will it be to get the biggies to adopt this approach?


    We think that the biggies (especially Analog-centric semi’s) will come to realize the advantages of efabless’s crowdsourcing model over the traditional R/D model for product development. The adoption by the “biggies” will be limited by their own reluctance to embrace open innovation and crowdsourcing.

    Our initial goal is to address markets that the big companies do not serve well – i.e. custom - and enable a far broader group of designers – individuals to small firms – to create designs and respond to requests. We are opening new markets – filling gaps in IP at foundries and ASICs, including for new markets like IoT

    2. What happens to optimizations of the IP? Semicon companies like the architecture licensing model (for the big IPs) because it gives them the freedom to tweak/optimize the uArch under-the-hood (competing over core-count, clock-freq, pipeline-depth, cache sizes and strategies, power-modes, etc.). Assuming that buying open-source IP provides standard flavours, it isn't always easy integrating them all to form a tightly-coupled system, implying that semicon companies can no longer tweak to get their "optimum".

    We believe that over time the community will tweak and customize the IP modules and respond to customers that need IP derivatives, variants or retargeting new markets or technologies.

    My guess (from limited knowledge) would be that crowd-sourcing of semiconductors would work well if:

    1. The designs are targeted to being cheap. IoT is a good example, where platforms need to be simple but robust.
    2. Semicon companies stop running rat-races with each other, and instead, collaboratively build an ecosystem where such a methodology would succeed.

    Bingo. We certainly agree on the first point. Add to that the need for mass customization for many niche applications and products that no one knows which will be the “killer product”.

    On the second point, we believe that Semicon’s that continue to adopt traditional innovation models will be held back by the massive inertia and will not be economically positioned to adapt to the massive variety of custom products for the next generation IoT solutions.

    It is time semiconductor industry go the open source way..great move !

    Agree. BTW, our platform is open innovation…a community working together to solve problems. The solutions may be open source. We will support open source and our bet is that this will grow over time.

    As programming is one of my hobbies and I am an open source proponent I needed to test this. Of course looking from an open source hacker standpoint. Although they market themselves as the github for ASICs the side does not feel like github:

    • Needed to register to be able to do anything on the site. On the contrary github projects are browsable by anyone.
    • Also the section is called 'IP/IC marketplace' not 'IP/IC Hub' which for an open source proponent does not feel like hacker friendly but commercial.
    • Currently my registration is pending as it has to be reviewed, this also feels very unnatural. It seems the legalise is still rippling through.


    So first impression is that efabless is likely the right step in the direction of low-volume/low-cost ASICs but in my humble opinion trying to present themselves as the github for ASICs is not wise. It gives expectations they don't currently meet as they want more control on the IP than github takes over it's open source projects (e.g. none).
    Likely to be continued when account is approved.


    Your observations are right on. The visible message on the site does not align with the github analogy. We acknowledge that. Thank you. You will see us converging very quickly (within weeks) to an overall offering that has:

    1. A github-like openness for the design IP – as a “IP/IC Design Hub” with specific focus on Analog/Mixed-signal IP
    2. A complete foundry-supported design toolset to enable designers to adapt, implement and prototype their work based on the sourced IP.
    3. A customer focused marketplace for community-developed finished hard IP that originated from the design-hub.

    github for ic or ip, that sounds like opencores.org to me, which has been around for several years. will be interesting to have two of them, like sourceforge and github?

    We are fans of opencores.org and there is synergy as their focus is on digital IP.

    efabless’s offering provides a full path from open IP to sold silicon designs. Lowering the barrier for designer community to reach prototypes that can enable effective showcasing of the design work to the customers. The platform has three main pillars:


    1. A github-like openness for the design IP – as a “IP/IC Design Hub” with specific focus on Analog/Mixed-signal IP
    2. A complete foundry-supported design toolset to enable designers to adapt, implement and prototype their work based on the sourced IP.
    3. A customer focused marketplace for community-developed finished hard IP that originated from the design-hub.

    Their tag line appears to be:

    Welcome to the world's first Community-Powered Analog IC Design Place
    which I guess answers the criticism that it's opencores.org all over again; not a lot of analog in there!

    But, like others, I do find the page awfully sparse on details. I'm left full of questions:
    * Toolset: They mention having one on the page, but how far does it go? Schematic, layout, DRC, LVS, extraction? How many do they have currently and what is "coming soon"?


    Acknowledged on the sparse nature of the information. We developed and will be offering a complete set of design software including system design, schematic entry, spice simulation, layout editing, DRC, LVS and parasitic extraction. Also a complete RTL-to-GDS digital design flow that includes synthesis, STA, placement and routing.

    We will also publish reference designs that can be “forked” and modified to community or customer application.

    We chose to gradually roll out the design flow capabilities over the next 3 months. Primarily paced by the availability of documentation and “How-To’s” that enable the designers to hit the ground running. We released the analog design entry & simulation. Coming next is digital design flow and analog layout and physical verification. Stay tuned and thank you for your comments.

    * Community: They mention free-lancers and consultants on the home page, so I guess that answers that question, but is it enough? I seem to recall having contracts under full-time employment with terms that say my brain belongs to The Company, pretty much.

    If someone wants to go free-lance, with this site as their Great White Hope for finding business, can they open an account to just fiddle and learn the tools?


    Yes

    * Fab and Testing: What I know about the IP business is that potential customers always start with the same question: is it silicon proven? And that is where the money comes in. Shuttles cost an awful lot! Do they intend for teams to fund collaboratively, with everyone chipping in? Are they aiming to have a monthly Top Ten go on a shuttle or something like that? And fabrication is only the first part. Customers also expect to see post-silicon test reports. Where's the lab? I suppose you can just ditto everything I said about paying for fabrication with testing.

    Shuttles: efabless offers what we call Leave-When-Full shuttles that allow flexibility on the time line for the tape-out to ensure a highly utilized shuttle space. That approach, along with efabless’s direct connection to the foundries, without a middle-man or an aggregator, brings the shuttle cost per mm2 within the low to high $100’s depending on the process technology. Keep in mind we focus on technologies like 180/130nm BCD and more mature 250/350nm with higher voltage support.

    Characterization & Testing: as a key part of efabless’s offering, we designed an open source HW platform board, along with reference ASIC designed to enable characterization of community IP. The design has been silicon-proven with our platform and will be announced to the world within few weeks. The designer can fork the test ASIC and replace the template design, with own IP and utilize the board and wakeup SW as or fork and adapt to their specific design requirements.

    For the labs – efabless is actively building partnerships with labs and test facilities that support low volume in different geographical regions. Through such partnerships the design community, individuals or companies, can access the the capabilities as a part of the eco-system efabless is providing.

    Stay tuned as we publish our progress on this front. Thank you for your patience.

    Also read: efabless: Think GitHub for ICs and IP