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  • STT-MRAM – Coming soon to an SoC near you

    An increasing percentage of SoC die area is being allocated to memory arrays, as applications require more data/instruction storage and boot firmware. Indeed, foundries invest considerable R&D resources into optimizing their array technology IP offerings, often with more aggressive device features than used for other IP (e.g., specific SRAM bit cells) and/or with unique process options altogether (e.g., embedded DRAM, non-volatile memory technology). Yet, what are the characteristics of an ideal SoC array? Is there a single technology option that could cover all or most of the application requirements?

    Article: A Brief History of Semiconductors-holy_grail.jpg


    The holy grail of an IP memory offering would provide:


    • high density
    • low additional cost, ideally leveraging an existing CMOS process with minimal FEOL changes required and minimal additional masking layers
    • low power (active power, and especially, leakage power)
    • fast read access time, random access/addressability
    • non-volatility (with long retention)
    • low wear-out (very large number of write cycles)
    • thermal stability
    • high yield, high reliability
    • low error rates, low susceptibility to an event upset

    An integrated circuit memory technology that has been actively researched for several years is magnetoresistive RAM, or MRAM, for short. As will be discussed briefly below, there is an evolving MRAM technology option that represents many of the preferred characteristics listed above.

    At the recent DAC conference in Austin, I had the opportunity to chat briefly with Kelvin Low, Senior Director Foundry Marketing, at Samsung Semiconductor. He was extremely excited (and justifiably proud) to highlight the Samsung exhibit demonstrating a pre-production silicon implementation of a 28nm STT-MRAM array. This offering will be available to Samsung Foundry 28FDSOI customers in 2018.

    There are some recent, commercial MRAM memory parts available, but to my knowledge, this is the first IP availability announcement by a major foundry for SoC customers.

    STT-MRAM Introduction

    Unlike traditional IC array technologies, MRAM does not rely upon the presence/absence of (active/dynamic) electrical charge on a storage node, but rather on the polarity of a local magnetic moment in one or more materials. The operation of the memory is current-based, rather than voltage-based.

    A write current is applied to set the magnetic moment orientation at the memory bit location. A (lower) read current senses the magnetic polarity. The magnetic moment orientation modulates the electrical resistance through the material layers – that resistance difference is non-destructively sensed during the read cycle. The technical developments in the disk drive industry – and disk drive heads, in particular – is being applied to integrated circuit processing. (Or, for us old-timers, think back to magnetic core memory technology.)

    There are several MRAM technology options that have been researched. The specific method used to “flip” the orientation at the array bit location is primarily what differentiates the various MRAM technologies.

    Article: A Brief History of Semiconductors-mram_fundamentals.jpg


    Samsung has selected the Spin-Transfer Torque method (STT-MRAM), as illustrated above. The STT-MRAM bit cell consists of a sandwich of three materials. The base or fixed layer is magnetically strong. (There are actually multiple material layers deposited and patterned for the fixed layer, which are simplified to a single layer in the figure.) A very thin electrically-insulating material – i.e., a few atomic layers thick – separates the fixed layer from the free material layer, which is magnetically weak. The magnetic polarity of the free layer will define the bit storage value.

    As the function of the cell utilizes electron tunneling through the thin intermediate layer, the STT-MRAM cell is also commonly denoted as a magnetic tunneling junction (MTJ).

    Electrical connectivity to the cell is provided by a traditional access transistor, leveraging existing CMOS processing. The STT-MRAM materials are added later in the overall process flow, residing above the transistors, minimizing the FEOL process disruption. The unique circuit topology of the STT-MRAM is illustrated below – in addition to the conventional array word line and bit line, the MTJ is connected to a sense line, due to the current-based operation.

    Article: A Brief History of Semiconductors-architecture.jpg


    The operation of the STT-MRAM cell relies upon the behavior of electron tunneling through a thin dielectric, as mentioned above.

    Simplistically (and with apologies to my quantum mechanics professor), the ferromagnetism of a material derives from the presence of unpaired electrons in the atoms, and thus, unpaired electron spin. The localized motion of these unpaired electrons results in a net atomic orbital magnetic vector (magnitude and direction), which applies a torque on adjacent atoms to align.

    Article: A Brief History of Semiconductors-write_parallel.jpg

    Write cycle for parallel magnetic orientation (Source: Samsung Foundry)

    Article: A Brief History of Semiconductors-write_antiparallel.jpg

    Write cycle for anti-parallel magnetic orientation (Source: Samsung Foundry)

    The STT-MRAM bit cell utilizes this general property of electron spin and magnetic vector angular momentum to establish the magnetic moment in the free layer. Referring to the figures above, application of a write current through the STT-MRAM cell cross-section from free layer (FM2) to fixed layer (FM1) is achieved by electron tunneling through the dielectric from FM1 to FM2. Electrons now present in FM2 with the prevalent spin orientation from FM1 will apply a net torque, with the net result of an overall parallel magnetic orientation between the two layers at the end of the write cycle.

    A cell write current in the opposite direction is a little more complex, as it depends upon the spin-dependent transmission and reflection coefficients at the FM1 material interface (within ~1-2 atomic lattice constants) of each of the two electron spin states originating from FM2. The net is that an anti-parallel magnetic moment orientation will be present in the two layers at the end of the write current cycle.

    The read cycle current through the cell is significantly less than the write current that is required to set the magnetic orientation in the free layer. The key feature is the difference in the electrical resistance through the cell, depending upon whether the orientation is parallel or anti-parallel. This resistance difference and the read current results in a voltage differential that is sensed to determine the cell stored value.

    Tunnel Magnetic Resistance ratio = (R_anti-parallel – R_parallel) / R_parallel

    Referring again to the ideal memory IP characteristics list above, an STT-MRAM memory array indeed represents many of the desired properties.


    • A DRAM-like single access-transistor cell with storage node for high density – check.
    • Low power – check.
    • Fast (non-destructive) read access time – check.
    • Non-volatility – check.
    • High reliability, with low wear-out (e.g., no charge-pumped, high-voltage write operation required) – check.

    As the STT-MRAM IP technology approaches production qualification at Samsung Foundry, look for additional Semiwiki articles with more technical details.

    For now, it would be worthwhile to envision how your future products could leverage the unique characteristics of this array offering. Indeed, before long, the MRAM acronym may just as easily signify “Must-have” RAM.

    For more details about Samsung Foundry technology, please follow this link.

    -chipguy