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  • Circuit Simulation Panel Discussion at #53DAC

    Four panelists from big-name semiconductor design companies spoke about their circuit simulation experiences at #53DAC in Austin this year, so I attended to learn more about SPICE and Fast SPICE circuit simulation. I heard from the following four companies:

    • Samsung
    • Oracle
    • STMicroelectronics
    • Qualcomm

    This panel discussion was hosted by Synopsys and of the big three in EDA they have more circuit simulators than any other vendor, both through internal development and acquisitions. Farhad Hayat was the moderator, and most of the time was spent with the panelists presenting their design challenges and approaches. The circuit simulation market is certainly a very competitive one, so it's always important to hear directly from users about which tool they used for each design and verification task.

    Simulation Technique for Thermally Aware 3D TSV IC Stacking-20160606_113642.jpg

    Related - Custom IC Layout Design at #53DAC

    The first panelist was Zach Coombes, from Samsung's Austin R&D group. They are responsible for the design of high end ARM-based CPU cores plus low power SoCs. As a CAD engineer he supports circuit simulators like FineSim, and the front to back-end design methodology. Their group also does custom circuit design, standard cells, physical implementation, custom SRAMs and they use technology nodes like 14nm and 10nm.

    Some of their design challenges include: Lots of corners for sign off, power grid extraction, interconnect extraction, and the parasitics of FinFETs.

    They have used many different SPICE circuit simulators and timing tools before, like: HSPICE, TimeMill, HSIM. FineSim is showing the overall best accuracy, and has a linear speed up with added CPUs. FineSim is now used for all of their SPICE simulation because it is accurate and fast. FinFET simulations with SPICE simulators could slow down by 50% compared to the simpler planar devices, however the speed difference has now improved.

    To extract power grids and then run IR simulations often slow down most simulators, while the latest FineSim is up to the task. Using 8 cores with FineSim shows about a 3X to 7X speed up, depending on FinFET technology. These multi-threading results are competitive with other circuit simulators available.

    A fast corners featured has recently been added to the simulator, so it learns with each PVT corner run.

    When using FineSim options to tune for SRAM designs they discovered that even the default settings matched what Samsung wanted to optimize.

    Sam Lo from Oracle is a hardware development manager, and his group is responsible for library characterization, SPICE circuit simulator, CMC and the Liberty TAB. Sam's group designs the SPARC servers, secure chips and the SPARC M7 (32 cores, 8 threads per core, 4.13 GHz, 20nm).

    The SRAM used in cache was 64MB L3 cache and a 256KB L2 cache, both using multiple Vt devices. For circuit simulation they used: CustomSim, HSIM, NanoSim, StarSim-XT (past 15 years). With the new FinFET SRAMs they see much larger netlists, more device parameters, more dummy transistors, more parasitics and Polycide on Diffusion Edge devices (PODE).

    CustomSim is used for the simulation of SRAM designs at 20nm and FInFET designs. WaveView is their viewing tool. Macro commands were used, and also characterization commands to automate the design flow.

    The total number of circuit simulations required during design and characterization is increasing: more states, statistical variations, more corners. Self-heating Effect (SHE) - FInFET effect, affected by the poly gate location is another challenge and at first the circuit simulations slowed down by 6X with SHE, but now the simulation speeds are back to normal.

    Sam's group found that CustomSim was about 3X to 30X faster than Golden simulation results, with an acceptable accuracy. A big challenge with FinFET devices is the increase in number of parasitics compared to the previous planar transistors, which in turn is taxing circuit simulation run times.

    The third panelist was Atul Bhargava and his group does Analog IP designs, like: clock generators, data converters, interfaces, PHY, RF, power management. They make use of SAE, the Simulation Analysis Environment where you run and control simulations from inside of the Custom Compiler tool. They start Monte Carlo simulations within SAE to run CustomSim, then use distributed processing to parallelize all of the separate simulations.

    Parasitic resistances get extracted and are a more important effect to analyze now. Monte Carlo simulations show that local effects need to be accounted for to get the desired accuracy and functionality. Fast SPICE is required to get enough simulations done in time. Their circuit designers are viewing data with both histograms and data plots to understand results more quickly.

    CustomSim is producing results within a few % of their golden SPICE results, although at a much faster speed. Reliability testing like the effects of aging are simulated with CustomSim, and the results are within 6% of SPICE at a 30X speed up to SPICE. Memory characterization and Monte Carlo simulations are all controlled from within CustomSim now.

    Our last panelist was Bramha Marathe, who also happens to be a published author. Bramha's group designs the SnapDragon chipset, and they define all of the AMS verification for: SerDes, PHYs and power management.

    AMS verification methods are really catching up with digital verification. For AMS functional verification they look to catch any interface issues between A and D, model verification, assertion checks in analog domain, and having independent verification from design.

    They have a real need to verify their power estimation - versus Frequency, Voltage and Temperature.

    With a traditional verification flow they are using UVM agents. They are starting to take their digital verification environment into the SPICE world. With VCS AMS they can save a snapshot of the first run, then reuse that saved point in subsequent runs, saving long run times. Their group also uses VCS AMS plus XA simulations in this flow. Both asynchronous and synchronous assertions can be used with AMS designs. They can even use functional coverage and SystemVerilog commands for node voltages.

    Using AMS test plans they can run gate level simulation with SDF at the AMS level to provide added confidence on the A and D interface timing at targeted corners.

    Synopsys has some 600 AMS R&D users internally that use the various circuit simulators (CustomSim, FineSim, HSPICE) along with Custom Compiler. The new simulation environment abbreviated as SAE is now included free of charge to anyone that has an existing circuit simulator from Synopsys, and this tool lets you setup testbenches, manage simulations and gather all of that data for visualization and analysis. The designers on the panel noted the challenges of AMS design and how the various Synopsys circuit simulators are being used to analyze and characterize a wide variety of circuits.