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  • Semiconductor IP QA Standards Get a Boost at #53DAC

    At the #53DAC earlier this month held in Austin, Texas I met up with Renee Donkers, the founder of Fractal Technologies. His company has been focused on improving the quality of semiconductor IP cells through the use of automated checking software. The highest area of growth in EDA as measured by the ESD Alliance is in the reusable IP cells being provided by IP vendors, so it makes sense that we really need an independent method for validating the quality of IP blocks and all of their files for correctness and consistency.

    Article: A Brief History of ASIC, part I-fractal-technologies-min-jpg

    Q&A
    Q) What's new this year at Fractal?

    This year we are introducing Transport at DAC, our new formalism for describing IP QA standards. Within Transport IP integrators can capture their QA requirements as they are checked by Crossfire for handoff to their IP suppliers. The way you use Transport very much resembles how a DRC-deck is used between a foundry and its customers.

    Related blog - DRC Concept for IP Qualification and SoC Integration


    Q) What type of engineer uses Fractal?

    Typically both IP designers and IP integrators use Crossfire. An IP integrator uses Crossfire to do incoming inspection of an IP block before it is integrated in the design, again using the checks as specified in Transport. IP designers use Crossfire throughout the entire IP design-flow to ensure that quality issues are detected as close as possible to their creation. This enables very short repair cycles and leads to an increasing level of robustness throughout the IP design flow.
    Article: A Brief History of ASIC, part I-crossfirevalidationengineschema-min-jpg



    Q) Where does Fractal fit into my IC design flow?

    Anytime a new part of the IP database is created or modified offers a potential insertion point for Crossfire usage. This can be the creation of a Verilog simulation model, the output of a characterization run, the conversion of layout views in the LEF and other routing abstract views as well as the datasheets that are created. All of these new formats and databases can be checked for consistency and completeness using Crossfire.


    Q) What problems can I solve by using Fractal tools?


    Crossfire and Transport solve the problem of delayed design cycles due to all kinds of IP inconsistency issues that are normally only detected during final design verification before tapeout. Only at that stage all different views are assembled into an SoC wide representation of the design and checked for correctness. An LVS check is the one of the best known examples: a missing terminal in a schematic view may lead to difficult to trace errors that can jeopardize the entire tapeout schedule.

    Crossfire keeps the bug-repair feedback cycle short by checking every new component of an IP database directly at the point of creation. At that point issues are easy to fix, the experts are still involved with the design-creation and none of the problems is obfuscated by design-size and complexity.


    Q) Are your tools approved by any of the foundries (TSMC, GF, UMC, SMIC, etc)?

    Also foundries use our tools these days, including some of the ones you mention. What we see is that usage of Crossfire at the moment is mostly promoted by foundry customers. These include that largest customers from the foundry list above.

    Foundry customers need to integrate IP, often from different vendors, into their designs and have to make sure that their IP deliveries are internally consistent and are compatible with the design-tools they use.

    Ideally our major fabless customers are pushing to get global Foundries enablement, but if we expect that it is going to take a couple of more years to get a complete coverage.


    Q) Do you have any paper presentations at DAC, workshops or panel discussions?


    Not this year.


    Q) What kind of companies are using Fractal tools?

    Any company using or designing IP. This includes basic cell libraries, Hard IP blocks including analog and soft IP cores.


    Q) Why is attending DAC useful to Fractal?

    It's giving us a great opportunity to meet face-to-face with our customers, demonstrate our latest release and collect inputs from customers on where they see the industry developing and the concerns they have on the IP qualification for their next designs.


    Q) What have you learned at DAC this year?

    As expected fewer visitors compared to DAC in San Francisco. Another interesting observation is that besides the big 3 EDA vendors, apparently data management companies (IC Manage, Cliosoft, Methodics) are doing well, while the number of EDA companies seems to decrease every year. Will be interesting to see who will disappear in the next 12 months before we again go to Austin.

    Article: A Brief History of ASIC, part I-20160607_151253-min-jpg