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  • IMEC Technology Forum (ITF) - EUV When, Not If

    Article: A Brief History of Semiconductor IP-asml-euv-lithography-min-jpgFor me personally EUV has been something of a roller coaster ride over the last several years. I started out a strong believer in EUV but then at the SPIE Advanced Lithography Conference in 2014 TSMC gave a very negative assessment of EUV, and there was a SEMATECH paper on high NA EUV that struck me as extremely unlikely to succeed. I also had one of the most knowledgeable lithography experts I know telling me he didn't think EUV would ever happen.

    You can read my blog about the 2014 Advanced Lithography Conference here.

    This year at the SPIE Advanced Lithography Conference the general assessment of EUV was much more optimistic. Source power is increasing and after many years of missed targets is following ASML's projections, pellicles are making progress and photoresists are getting more sensitive and capable. There are several sites around the world exposing thousands of wafers with EUV and nothing drives learning like running large numbers of wafers. Probably the biggest remaining issue is Line Edge Roughness (LER).

    I have published several blogs about the 2016 Advanced Lithography Conference here, here, here and here.

    Since the Advanced Lithography Conference I have heard that high source power EUV systems are damaging the masks. EUV masks are reflective and they absorb a significant amount of the incident EUV energy and could be subject to thermally induced strains particularly at high power. I should note here that I have asked several experts about this and they have all denied this is an issue.

    This week I was at the IMEC Technology Forum (ITF), IMEC is a technology research center located in Belgium that is one of the premier semiconductor research centers in the world today. The ITF is a two-day event attended by approximately 1,000 people to showcase the work done by IMEC and their partners.

    I have already published one blog about the ITF and I have more blogs in process but I wanted to focus on what I learned about EUV in this blog.

    My first blog about the ITF is available here.

    In the first talk at the ITF, Luc Van Den Hove, the president and CEO of IMEC said that we will need a cost effective lithography and EUV is the only solution they see. He is convinced it will succeed.

    During a panel discussion a question was asked about EUV and Gary Patton, CTO and Senior Vice President at Global Foundries said we will see it by the end of the decade although we may not take full advantage of the technology. In the same panel An Steegen, Senior Vice President of process technology at IMEC said she thought we would see it much sooner although we may need line smoothing technologies.

    As I have thought about what I heard this week I realized that the EUV we will likely get is very different from the EUV we originally expected.

    The history of microlithography is one of periodic shrinks in wavelength as we produce smaller and smaller feature sizes. G-line lithography with a 436nm wavelength gave way to I-line at 365nm at the 800nm node, KrF at 248nm took over at the 350nm node, ArF at 193nm took over at the 90nm node and ArFi with an effective wavelength of approximately 131nm took over at the 40nm node. At the beginning of the development of EUV the idea was to transition to 13.5nm EUV as the next progression in microlithography and use it for all critical layers.

    But then EUV was delayed and Multi-Patterning (MP) was developed to continue shrinking minimum dimensions until EUV is ready, except MP just keeps getting better and has proven to be particularly good at producing low LER values critical to the Front End Of Line (FEOL) transistor fabrication. So what does this mean for EUV? I think the bottom line is that the single exposure EUV for all critical layers' expectation is no longer going to happen and what we are likely to get is a hybrid MP/EUV solution.

    In an interview with Gary Patton that I will blog about later he said he thought EUV would be used for contact and via first and then metal layers.

    If you look at contacts and vias the MP at 14nm is done with Litho-Etch Litho-Etch (LE2), then for 10nm Litho-Etch Litho-Etch Litho-Etch (LE3) with the prospect of LE4 at 7nm. EUV is generally believed to be intermediate in cost between LE2 and LE3 so for 10nm and 7nm processes a single EUV exposure for contacts and vias would be cost effective. Contacts and vias are also not very sensitive to LER which is the biggest weakness of EUV.

    After contacts and vias critical metal layers are next. In the Front End Of Line at very small feature sizes Self Aligned Quadruple Patterning (SAQP) is used with cut masks. SAQP creates lines and spaces with a pitch down to 20nm and then cut masks cut the line ends. LER is excellent but for logic devices 4 to 5 cuts masks may be required for the 7nm node. For critical metal layers in the Back End Of Line the situation is even more complex. In BEOL applications block masks are used. In the FEOL with multiple cut masks you put on a cut mask, etch it into the hard mask, strip the cut mask, print a new cut mask and etch it into the hard mask over and over until you get the pattern you want in the hard mask. You then etch the hard mask pattern into the underlying film. In the BEOL you are creating trenches and you need block masks to block etching into the hard mask. The problem is that when you need multiple block masks the etch following the first block mask removes the hard mask from places where you want to apply additional blocks masks. The work around for this adds a lot of process complexity. With EUV you can do SAQP with a single EUV block mask and cut out a lot of process complexity. Since all you are doing is terminating the ends of the trenches you once again have an application that is less sensitive to LER.

    Finally, EUV could be used in the FEOL to replace multiple cut masks and once again if it is only cutting the lines, LER is less of an issue.

    There is another interesting aspect to EUV I hadn't really thought about much before this week and that is the affect it has on cycle time. If you replace 3 or 4 cut or block masks or 2 or 3 LE3/LE4 masks and associated processing with a single exposure you save a lot of cycle time. During my interview with Gary Patton he mentioned that Global Foundries is using EUV in place of MP for non-transistor layers during their 7nm development to save time!

    The sense I have now is that EUV will likely be implemented on a second generation 7nm technology and then with expanded use at 5nm, first at contact/vias, then for critical metal layers block masking and eventually it may be used for FEOL cut masking. For everything but contact/vias it will be paired up with SAQP to do blocks and cuts.

    There is also the prospect that LER improvement for EUV could expand the application space. There is a belief that as you lower the EUV exposure dose Shot Noise creates LER and that there is a fundamental trade-off between dose and LER. I asked An Steegen this question and she said it is more complex than that and that there is a lot of research being done on understanding the fundamental causes of LER. It is also possible to implement post lithography line smoothing techniques. Simply put, etching tends to remove peaks from roughness and deposition tends to fill in valleys. There is the potential to develop combination etch/deposition technique that smooths LER.

    The bottom line is that some of the leading process experts in the world believe EUV is coming before 2020, it just won't be the single exposure all critical layer EUV we were expecting when EUV development started and MP is likely here to stay.

    Also Read: IMEC Technology Forum (ITF) - IC Innovation