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  • Stop FinFET Design Variation @ #53DAC and get a free book!

    Article: Measuring the Accuracy of a 3D Field Solver for IC Extraction-stop-design-variation-min-jpgIf you plan on visiting Solido (the world leader in EDA software for variation-aware design of integrated circuits) at the Design Automation Conference next month for a demonstration of Variation Designer, register online now and get an autographed copy of “Mobile Unleashed”. Such a deal!

    Solido Variation Designer is used by 1000+ designers across 35+ major semiconductor companies to solve key production design challenges in memory, analog/RF, and standard cell design.

    REGISTER HERE

    Solido will be demonstrating the newest version of its software just released in March, Solido Variation Designer 4. Variation Designer 4 has advanced Solido’s state-of-the-art technology to tackle the latest variation-aware design challenges in nanometer processes including FinFET, FDSOI, low-power & low voltage.

    The following demonstrations are available:

    Solido Variation Designer for Memory
    Full Chip Memory and Cell Level Statistical Verification
    Solido Variation Designer delivers the most advanced and industry-proven technologies for statistical design & verification of memories:

    • Hierarchical Monte Carlo: Verify full-chip memories with perfect statistical accuracy
      • Statistically correct verification of replicated structures
      • Correct application of both global and local variation

    • High-Sigma Monte Carlo: Verify columns, bitcells, sense amps, and other memory blocks to high-sigma quickly and with perfect Monte Carlo and SPICE accuracy
    • Accurately verify production-sized designs (such as memory columns and critical paths)
    • Solve pass/fail, binary, and multi-modal output measurements
    • Efficiently debug high-sigma variation problems
    • Generate trustworthy high-sigma verification results

    Solido Variation Designer for Standard Cell
    Variation-Aware Verification of Cell Libraries
    Standard cell designers use Solido Variation Designer to accelerate the verification of their standard cell libraries across variation. The key technologies are:

    • High-Sigma Monte Carlo: Monte Carlo & SPICE accurate high-sigma verification of standard cells
      • Fast and accurate verification to high-sigma
      • Accurately capture performance and power vs. sigma tradeoffs for the entire sigma range
      • Batch operation for creating customized library verification flows

    • Fast Monte Carlo: Fast, accurate statistical verification of standard cells
    • 3-sigma verification & corner extraction
    • Batch operation for creating customized library verification flows

    Solido Variation Designer for Analog/RF and Custom Digital
    Statistical & PVT Verification and Debug
    Solido Variation Designer gives analog designers the ability to design with greater speed, accuracy, coverage, and insight than ever before:

    • Statistical PVT: Unprecedented accuracy and coverage across 3-sigma statistical variation and operating conditions
    • Fast PVT: 2-50X faster verification across corners & operating conditions
    • Fast Monte Carlo: Fast, accurate 3-sigma verification & corner extraction
    • High-Sigma Monte Carlo: Monte Carlo & SPICE accurate high-sigma verification and design of analog/RF and custom digital circuits.
    • DesignSense: Variation-aware sensitivity & design debugging.


    There is also a Variation-Aware Design DAC Panel with ARM, IBM, Invecas, and Solido on June 6. Plus Solido is presenting at the TSMC DAC Invited Theater Presentations (Monday to Wednesday June 6-8) and the Samsung DAC Invited Theater Presentation (Monday June 6).
    Article: Measuring the Accuracy of a 3D Field Solver for IC Extraction-solido-tsmc-webinar-jpg
    If you are not attending #53DAC you can attend the TSMC and Solido "Collaborate for Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes" webinar:

    Date:
    June 1, 2016
    Time: 10am Pacific
    Duration: 55 minutes

    Click here to register!

    Abstract:

    Variation effects have an increasing impact on advanced process nodes, and at each, new sources of variation must be considered. Furthermore, increased competition is forcing tighter design margins to make high-performance, low-power, low-cost products. Designers must now do more variation analysis than ever to achieve these tighter margins, using advanced variation-aware technology for speed, accuracy and coverage to deliver competitive chips on schedule. This webinar will discuss on how TSMC and Solido collaborate to offer variation-aware design techniques for memory and standard cell with TSMC advanced processes using Solido’s new Variation Designer 4.