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  • Webinar alert - VHDL guru says its time to move up

    Many years ago when I worked for Ed Staiano at Motorola, I learned never to use the word "comfortable" in a career context. Iím comfortable being with family and friends. This new high-back chair I sit in at my new faux-cocobolo desk (slightly distressed chalk-painted wood and industrial piping, awesome) is comfortable, a lot more so than that camp chair I was on for a few months. Itís comfortable inside this air conditioned house on a humid day. But Iím never, ever comfortable with my knowledge, competitiveness, or position at work. Andy Grove may have written the book, but Ed lead the choir on comfort leading to complacency.

    Engineers tend not to operate that way (unless they encounter one of these managers or their disciples). Expertise has a high value. Years of investment in learning every detail of a skill lead to more opportunities to use that skill. That works for a while, perhaps even decades, until it becomes time to upgrade skills. COBOL programmers are still out there, but they donít get a lot of new opportunities unless they learn something more on the cutting edge.

    Article: Mars Rover "Curiosity" and EDA-vhdl-systemverilog.jpgI can see engineers being extremely comfortable with VHDL. It's tried, and proven, and still usable. But it's the 21st Century and all, and there are new standards and new tools and people getting better results in chip design. Resisting a move to SystemVerilog and UVM, now both in wide adoption and growing, can be a career limiter.

    So when the author of "VHDL: Programming by Example" speaks on a webinar providing a look at SystemVerilog and contrasting its features and use with VHDL, itís time to move up. Doug Perry is working at Doulos these days as a Senior MTS, and he may be the biggest of the VHDL gurus left Ė many VHDL designers have his book on their desk.

    Perry will walk through the challenges in making the transition from comfortable VHDL to the more modern SystemVerilog from his unique perspective, using examples running in Aldec Riviera-PRO. Registration for this May 4th webinar is free on the Doulos site:

    Getting into SystemVerilog from VHDL: Guidance from a VHDL Guru
    Europe and Asia time zones
    North America time zones

    If you haven't already made this move, take an hour and learn why you should from a guru.