Let's start with a 6 transistor SRAM cell schematic showing a Word Line (WL), Bit Lines (BL), PMOS pull-up transistors (PU), NMOS pull-down transistors (PD) and NMOS transfer gate transistors (PG):
One reliability challenge is that the Voltage Threshold (Vth) of both PMOS and NMOS transistors will change over time as the devices are turned on and off. For PMOS transistors the effect is called Negative-Bias Temperature Instability (NBTI) and for NMOS transistors its called Positive-Bias Temperature Instability (PBTI). With NBTI and PBTI the value of Vt increases over time and mobility decreases, causing the transistors to become slower.
Because an SRAM bit cell is very sensitive to device matching we really need to know how the Vth distribution changes over time. The minimum VDD supply level required to ensure proper write and read cycles is called Vddmin, and it's another critical metric for users of an SRAM instance.
Engineers at STMicroelectronics designed a test structure in 14nm FDSOI to characterize SRAM bit cells, then measured the difference in MOS values with fresh and aged parameters for both NMOS and PMOS transistors:
Correlation plots between fresh and aged parameters
For PMOS transistors we find that the spread is larger after aging than NMOS transistors, while the parameters are only shifted for NMOS transistors. The next chart shows how the Vth values are shifted for different stress times on the left, and on the right it shows that Vth shift is uncorrelated with the initial Vth.
The Vth distribution is still normal as shown below with devices i and j starting out at plus 3 sigma Vth and minus 3 sigma Vth, respectively. The worst Vth after a BTI stress is directly related to its initial Vth.
A BTI model can be developed to show the Vth shift and its final distribution.
Using this BTI model and then running Monte Carlo analysis on a 6 transistor SRAM bit cell to measure the Static Noise Margin (SNM) during write and read modes produces the next chart, along with a Worst Case Analysis (WCA) using the WiCkeD software from MunEDA:
Sensitivity analysis of local Vth parameters at a 5 sigma target for SNM reveals which device parameters are the major contributors. The contribution of ageing induced dispersion is moderate compared to the one of fresh Vth location variation, but is significant.
- Fast pull-down R
- Slow pull-up R
- Fast pass-gate R
SRAM Bit Cell Sizing
For optimal bit cell design we need to optimize SNM, Write Margin (WM), Iread (drive current during read) and Isb (leakage current). Fortunately for us there is an automated Yield Optimizer (YOP) that can attack this problem, instead of using manual, iterative efforts. Here's a screen shot of using the yield optimization from the WiCkeD tool for: Area, Iread, Isb, SNM, WM
Note how both WM and SNM grow in robustness during optimization, whereas their nominal values grow only little or even shrink. Such mixed effects between spec robustness, nominal value, and device geometries are common and are the reason why a yield optimizer has to run high sigma analysis repeatedly for all specs. Short runtime and high accuracy of the worst-case analysis are key for SRAM yield optimization.
You can even ask the optimizer to tune transistor sizes for low leakage, low power or high performance.
SRAM design is a tricky thing to use manual efforts and then get optimal results because of physical effects like BTI. STMicroelectronics has worked with MunEDA to create a methodology that automates transistor sizing of their SRAM bit cell while taking into account BTI effects on Vth values. This optimization helps create higher-yielding SRAM IP for use in SoCs built with FDSOI.