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  • IC Design Optimization for Radiation Hardening

    I was born in 1957, the same year that the Soviets launched the first satellite into Earth orbit, officially starting the Space Race between two global super powers. Today there are many countries engaged in space research and I just read about how engineers at IEAv (Institute for Advanced Studies) in Brazil did their IC design optimization for radiation hardening. The CITAR project has multiple institutions collaborating to create ICs for satellites used in the Brazilian space program:

    • Design ICs - Centro de Tecnologia da Informacao Renato Archer
    • Radiation Tests - IEAv, USP, FEI
    • End User - INPE


    Article: Addressing the Nanometer Custom IC Design Challenges! (Webinars)-collaboration-min-jpg


    In space there are cosmic rays that create trapped particles like protons, electrons and heavy ions. These particles effect ICs in orbit in a variety of ways:

    • Vth of the P and N channel MOS transistors will shift up or down
    • The sub-threshold slope increases
    • Leakage currents increase
    • Mobility is decreased


    Article: Addressing the Nanometer Custom IC Design Challenges! (Webinars)-radiation-effects-min-jpg


    Circuit designers need to know how these particle induced effects in satellites will change the performance of an IC over time. The Total Ionizing Dose (TID) defines the extent of radiation effects. Fortunately the researchers can create radiation models here on Earth by running radiation experiments. On this IC project the chip engineers optimized their circuits for use in a rad-hard environment by using an optimization tool called WiCkeD from EDA supplier MunEDA.

    Their old design methodology was updated to include rad-hard optimization using WiCkeD as shown below:

    Article: Addressing the Nanometer Custom IC Design Challenges! (Webinars)-design-methodology-min-jpg

    A bandgap circuit from the XFAB reference kit was optimized in this new design flow using the XH018 process. The specifications for this circuit are:

    Article: Addressing the Nanometer Custom IC Design Challenges! (Webinars)-specifications-min-jpg

    The goal is to load both the standard model and rad-hard model into WiCkeD, then optimize the circuit to pass all corner cases.

    Step one is to use this circuit with initial values of Width and Length devices at a nominal corner and see how the circuit performs against the specifications. They found that both minVBG and TC were violating the specification for this initial corner.

    Article: Addressing the Nanometer Custom IC Design Challenges! (Webinars)-initial-corner-min-jpg

    Step two is to run Deterministic Nominal Optimization (DNO) to improve the design so that it passes all specifications. After a few DNO iterations the circuit now passes the specifications:

    Article: Addressing the Nanometer Custom IC Design Challenges! (Webinars)-dno-results-min-jpg

    In robustness verification they found good results over all operating conditions. The yield estimated by 200 samples of Monte-Carlo Analysis is 99.5%, and a Worst Case Analysis showed that all specifications could be achieved with a robustness of at least 2.58 sigma:

    Article: Addressing the Nanometer Custom IC Design Challenges! (Webinars)-robustness-min-jpg

    Yield Optimization was the next step and this is where they ran corners with the fresh models and corners with the rad-hard models to see what the mismatch effects were. Robustness verification of Yield Optimization (YO) showed that all specifications could be achieved with a robustness of at least 3.21 sigma:

    Article: Addressing the Nanometer Custom IC Design Challenges! (Webinars)-robustness-after-yield-optimization-min-jpg

    Here's a quick comparison of device sizes after each optimization step:

    Article: Addressing the Nanometer Custom IC Design Challenges! (Webinars)-device-sizes-min-jpg

    The yield optimizer (YO) improved the robustness against random variation at worst-case corners, operating conditions, and radiation from 2.6 to 3.2 sigma without increasing the area, only be re-balancing the transistor geometries.

    Summary

    IC designers can optimize their circuits for rad-hard environments found in orbit by using EDA tools like WiCkeD from MunEDA. Engineers on this particular project took about two weeks elapsed time to optimize their circuits, taking about 18,000 simulations for the entire design flow.

    IRPS Conference

    On April 21st at the International Reliability Physics Symposium there's an interesting paper from STMicroelectronics and MunEDA titled, "BTI Induced Dispersion: Challenges and Opportunities for SRAM Bit Cell Optimization". This paper presents at 1:30PM and here's the abstract:
    One major CMOS reliability concern for advanced nodes is the Bias Temperature Instability (BTI) mechanism. In addition to the native local process dispersion, the BTI induced dispersion is a field under intensive research. Important works [1, 2] focus on the distribution tail of the Vth shift and efforts are deployed to high-sigma accurate modeling (defect centric, Skellam). In most applications influenced by devices matching (ADC, SRAM…), it is important to understand how the initial Vth distribution evolves in time. In this paper some key results of spread induced by BTI are reviewed for 14FDSOI and 28FDSOI from STMicroelectronics. Analysis between initial Vth and aged Vth correlation is presented. Then, measurement of fresh and post HTOL memory VDDmin is presented for different conditions of temperature and process centering. Finally, an innovative algorithm of yield optimization is presented. It enables to optimize the centering and yield (through devices sizing or process centering) including ageing, under constraint of foot print.

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