6T SRAM cell size versus node (µm2).
Looking at this data you can see that at 45nm and 20nm TSMC led and at 28nm Samsung led (the leaders at each node are in bold). At 16nm TSMC chose to take a conservative approach and leverage their 20nm process pitches for their first FinFET resulting in a larger SRAM cell size than would otherwise have been expected. Intel very aggressively scaled their process and took the lead.
I have taken 6T SRAM cell size data for Intel back to 130nm, Samsung back to 90nm and TSMC back to 130nm and plotted SRAM cell size versus node. Using a power law to fit the curves the R2 values are >0.98 for Intel and TSMC and >0.97 for Samsung clearly indicating a very good fit. Using the resulting equations, I have projected Intel and TSMC 10nm 6T SRAM cell sizes. For Intel I project a 6T SRAM cell of 0.0284µm2 and for TSMC of 0.0238µm2.
Assuming TSMC returns to their historical SRAM trends they will once again have the smallest SRAM cell size. This may be optimistic because Intel is expected to have a smaller contacted gate pitch and minimum metal pitch than TSMC at 10nm. In fact, we expect TSMC's 7nm process to have similar pitches to Intel's 10nm process. We should note here that TSMC is expected to begin ramping 10nm at the end of 2016 and they are targeting the end of 2017 for a 7nm ramp. With Intel delaying 10nm to 2017 TSMC's 7nm and Intel's 10nm may be ramping around the same time.
The bottom line is based on my analysis the Samsung 10nm 6T SRAM cell size looks significantly larger than what I would expect from Intel and TSMC.