You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • TSMC and Intel on the Long Road to EUV

    Who needs design automation?-intel-euv-2016-jpgToday is the first day of the SPIE Advanced Lithography Conference and Extreme Ultraviolet (EUV) updates were a big focus.

    Anthony Yen of TSMC – EUV Lithography: From the Very Beginning to the Eve of Manufacturing
    This talk was one of three plenary talks to begin the day. The talk began with a history of EUV development from the beginning in 1985 as Soft X-Ray to the name change to EUV in 1993, to today’s status.

    TSMC first signed on to EUV in 2008 and in October of 2011 completed installation of an ASML NXE3100 first generation EUV tool. In October of 2013 TSMC completed installation of a second generation NXE3300 and just recently received a new third generation NXE3350.

    The NXE3100 has shown 46nm metal pitches with a single exposure. A <50nm pitch via requires four masks for argon fluoride immersion (ArFi) system and can be done with one mask using EUV while achieving greater depth of focus. EUV has also shown 2D metal patterns with large lines except for one small space, ArFi can’t do that.

    EUV power at TSMC is running ~80 watts, ASML has shown 185 watts in Q4-2105 and 200 watts now.

    EUV collector reflectivity maintenance is getting much better running for ~3 months in an R&D fab.

    Over 4 weeks the NXE3300 has produced 518 wafers per day with 70.2% availability.

    Mask blank defects are ~20 per mask which is pretty good. The defects can be hidden by shifting the pattern.

    TSMC and ASML are using two steps to keep the mask clean. One is a dual pod to keep the mask clean out of the tool and the other is pellicle development for when the mask is in the tool. They have a full size silicon membrane pellicle 50 microns thick with 85% transmission. They want >90% transmission.

    A lot of progress has been made in photoresist development. Sensitivity of 38 mJ/cm2 has now been reduced to 27 mJ/cm2 with a goal of 20.

    A 0.33 NA tool will require multi-patterning beyond 5nm. ASML is working on a >0.5 NA anamorphic tool (4x reduction in one direction and 8x reduction in the other). The anamorphic tool is expected to offer higher throughput and resolution with better EUV optics transmission. ~170 wafers per hour with a 250 watt source and 25 mJ/cm2 photoresist.

    The current power roadmap is 80W in 2015 (complete), 250 watts in the 2016-2017 timeframe, >250 watts in the 2018-2019 timeframe.

    A lot of progress has been made in the last ten years.

    TSMC will not use EUV at 10nm, they will “exercise” EUV at 7nm, they plan to introduce EUV for production use at 5nm. First use will be for contact holes where mask defects can be more easily hidden by pattern shifting. Line/space patterns need <10 defects per mask blank.

    Britt Turkot of Intel – EUV Progress Toward HVM Readiness
    Later in the day this keynote talk provided an update on Intel’s EUV work.

    Two years ago the key issue were:
    1. Photoresist – line width roughness (LWR) and outgassing
    2. Tools – source power and availability
    3. Reticle – killer defects and pellicles

    Progress was needed on all three fronts.

    As of today photoresist sensitivity for reasonable patterns is good. Progress to 250 watts is good with 200 watts shown.

    Intel has an in-house micro field EUV tool with an NA of 0.5 that has produced wafers with a 22nm pitch!

    ASML power improvement is now tracking to the power plan with a 2x increase in power over the last year. The droplet generator is now achieving 85% of expected run time. Collector reflectivity degrades predictably.

    NXE3300 is being run 21 hours per day cycling wafers with 3 hours set aside for engineering on a 14nm pilot line. Availability out of 21 hours a day at 80 watts (60 watts actual) is ~70% and they are exposing 2,000 to 3,000 wafers per week.

    EUV overlay to ArFi tools is as good as ArFi to ArFi tool overlay. They have achieved stable 14nm CDs for over 7 months. EUV yields are as good as the ArFi process of record.

    The tin generator and collector lifetime and scanner and source are all showing solid progress.

    Multiple vendors are delivering single defect reticle blank defectivity (better than TSMC reported). Pattern shifting can be used to mitigate defects but actinic inspection is needed and it is difficult to implement. Defects need to be driven down further but a defect free 7nm via mask has been created from a blank with 6 defects. eBeam defect repair for masks is well established.

    Front side reticle defects are being reduced by 10x per years plus with new tools. Fall-on reticle defects are just over 0.04 per pass. They have demonstrated 1 critical defect for 20 stage loads. For comparison ArFi is 0 with a pellicle. A full field pellicle has been tested in the scanner with 200 wafers exposed at 40 watts. Pellicle defect inspection is in development. Pellicles have high defect counts and are very dirty but only 3 defects were visible on the wafer. No adders have been seen with pellicles. The availability of high quality reticles is the highest risk.

    Challenge towards breakage of RLS trade-off by new resist an processes for EUV lithography
    This paper was one of many papers given on EUV photoresist and was near the end of the day. I unfortunately missed the presenters name. The work was done by TEL, JSR, Osaka University, and ASM with several authors.

    RLS stands for resolution, line edge roughness and sensitivity. Creating a sufficiently sensitive photoresist is essential to achieving good EUV throughput.

    The process discussed here uses a photo sensitized chemically amplified resist (PSCAR) with a special process:
    • Coat the wafer with PSCAR
    • Expose the pattern on the EUV scanner
    • Flood expose the wafer (added step versus typical sequence)
    • Post exposure bake
    • Develop

    The process shows a 2.37x improvement in sensitivity with a 47 mJ/cm2 exposure being reduced to 19.9 mJ/cm2 with more process latitude.

    The flood exposure increases acid generation helping with contrast and allowing more quencher to be added.

    At 18nm half pitch a 16.9 mJ/cm2 dose looked OK and 30 mJ/cm2 looks very good. They also did 22nm and 16nm half-pitch with similar results.

    A 15nm half pitch line/space exposure looked good at 3.18 mJ/cm2 with a LWR of 3.9nm. CD uniformity with flood exposure went from 0.81nm to 0.62nm three sigma.

    Conclusion

    There were several other papers on EUV as well throughout the days but the key message is substantial progress is being made in all of the areas required for EUV to enter production use. TSMC is targeting 5nm for EUV insertion consistent with what we have heard from other foundries. There is still a lot of work to do but there are multiple EUV machines around the world now being run continuously to gather data and optimize the process.

    Other articles from Scott...