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  • New CEVA X baseband architecture takes on multi-RAT

    What we think of as a “baseband processor” for cellular networks is often comprised of multiple cores. Anecdotes suggest to handle the different signal processing requirements for 2G, 3G, and 4G networks, some SoC designs use three different DSPs plus a control processor such as an ARM core. That’s nuts. What is the point of having a DSP core if you have to have 3 of them, plus another core for control?

    Part of the issue is legacy. DSP IP was often developed and optimized for 2G, then again for 3G, then again for 4G, rather than stepping back and looking holistically at the baseband as an engine. Viewed as a whole, the driving requirements for a modern baseband engine lie in the complexity of the respective modem PHYs and the ability to switch between them with ultra-low latency – calling for an efficient combination of DSP and real-time control processing.

    With LTE B coming online (more accurately, LTE-Advanced Pro described in 3GPP Release 12 and 13) the PHY processing and control problem gets even bigger. A Rel 13-compliant modem may aggregate up to 5 carriers, each with their own measurement, calibration, and processing requirements. A modem may also pull from two cells, for instance getting control signaling from a macro cell and a better link budget for high speed data from a small cell.

    That suggests it is time for a new, more efficient processor architecture for baseband designs – one that handles DSP and real-time control effectively. Impossible, with disparities in word widths, pipelines, addressing modes, caching, and other details? Not for the company with DSP cores in basebands in 6B handsets to-date.

    Article: Laker Analog Prototyping-ceva-x4-architecture-min.jpg

    CEVA has gone back to the drawing board with its new CEVA-X Architecture Framework. It’s a scalable solution with three pieces. First is new DSP capability, 2x faster compared to the current CEVA-X1643, with up to 7-way VLIW, 128-bit SIMD with up to eight 16x16 MAC operations per cycle, up to four optional IEEE single-precision floating point units, a 256-bit memory path, and optional data and instruction cache. For control processing, up to four programmable scalar units (thus the name for the first IP offering, the CEVA-X4) optimized for context switching can be paired with dedicated CEVA-Connect hardware queue and buffer managers controlling the data flow in the PHYs without DSP intervention.

    The CEVA-X4 core announced at MWC 2016 looks formidable compared in tabular form to a Qualcomm Hexagon QDSP6 core. Comprehensive benchmarks are not yet available, but in EEMBC CoreMark results the CEVA-X4 delivers a CoreMark per MHz figure of 4.0, very close to that of the ARM Cortex-R7 core at 4.35, and way ahead of the QDSP-6 core at 2.4 per thread.

    Article: Laker Analog Prototyping-ceva-x4-vs-qdsp6-min.jpg

    source: CEVA, gathered from publicly available information

    Qualcomm has just announced its Snapdragon X16 LTE modem, not clear yet what the DSP suite inside is and it isn’t available in IP form for SoC designers. ARM has also just announced Cortex-R8, and they are obviously looking ahead at the same problem of real-time control of a multi-RAT (multiple radio access technology) configuration – but they would need to have some accompanying DSP core for the heavy lifting. It’s game on for Rel 13 modem designs.

    One point the introductory AnandTech article on the ARM Cortex-R8 raised was just how challenging it is to manage PHYs in a multi-RAT scenario. Designers would like this to be soft, but the speeds involved are difficult, particularly in achieving ultra-low latency. Creating hardware to manage the flow effectively is a big R&D task. The CEVA X hybrid solution may be the way out, combining the benefits of soft DSP and control with acceleration. CEVA-Connect can help manage memory bandwidth and offload transfers in independent task queues without DSP intervention.

    Article: Laker Analog Prototyping-ceva-connect-min.jpg

    Scalability is key for an IP offering; the CEVA-X4 can run flat out at 1.5 GHz in 16nm (!), or can be dialed back for a 40% smaller implementation than the ARM Cortex-R7 at less than Ľ of the power consumption running at 600 MHz in 40nm. Power consumption of the CEVA-X4 is 50% lower compared to the CEVA-X1643. Recognizing that not every solution will be on a cutting-edge process and that power is paramount, this may give CEVA an advantage.

    The CEVA X Architecture Framework puts a software solution capable of handling multi-RAT on a single baseband engine, handling LTE-B as well as LTE-A, 3G, TD-SCDMA, and 2G, plus VoLTE EVS. A software solution on a DSP with hardware acceleration such as this also looks ahead to 5G with het-nets and addition of Wi-Fi and many of the IoT-related specifications to the mix of requirements.

    For more information on CEVA X:

    Introducing The NEW CEVA-X - The World's Most Efficient Processor Architecture for Baseband Applications

    CEVA is issuing a challenge to the model that dates all the way back to the origin of the TI OMAP architecture with ARM+DSP – a formula baseband designs have followed since. Complexity is growing and available size and power aren’t. If CEVA can play its advantages in low-power IP into a hybrid architecture that makes heterogeneous cores in basebands unnecessary, this could be big for not only future smartphones but wearables and IoT devices.

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