WP_Term Object
(
    [term_id] => 21
    [name] => Ceva
    [slug] => ceva
    [term_group] => 0
    [term_taxonomy_id] => 21
    [taxonomy] => category
    [description] => 
    [parent] => 178
    [count] => 160
    [filter] => raw
    [cat_ID] => 21
    [category_count] => 160
    [category_description] => 
    [cat_name] => Ceva
    [category_nicename] => ceva
    [category_parent] => 178
)
            
CEVA PR Rebrand SemiWiki 800x100 231207 (1)
WP_Term Object
(
    [term_id] => 21
    [name] => Ceva
    [slug] => ceva
    [term_group] => 0
    [term_taxonomy_id] => 21
    [taxonomy] => category
    [description] => 
    [parent] => 178
    [count] => 160
    [filter] => raw
    [cat_ID] => 21
    [category_count] => 160
    [category_description] => 
    [cat_name] => Ceva
    [category_nicename] => ceva
    [category_parent] => 178
)

Who Does Voice Recognition in the Samsung Gear S2?

Who Does Voice Recognition in the Samsung Gear S2?
by Eric Esteve on 01-03-2016 at 4:00 pm

If you have bought a Samsung Gear S2 smartwatch for Christmas, you certainly didn’t open it to do a teardown. Chipworks did it and have shared the results: Qualcomm is the big winner here with five different chips: Snapdragon 400 as the main CPU of the system, the RF transceiver, the audio codec, the power and the baseband processor (MSM8226). Not really a surprise as the Qualcomm wireless port-folio is certainly the strongest in the industry.

Samsung has integrated three of its own chips, DRAM memory, NFC controller and Wi-Fi module, a DC-DC converter for AMOLED, accelerometer and gyroscope and barometer from STMicroelectronics and another DC-DC converter from TI. In fact, the real surprise comes from a chip from DSP Group HDClear family, especially dedicated to manage the audio command capabilities of Samsung Gear S2. At the heart of the DSPG HDClear is CEVA-TeakLite-III DSP core that DSPG has licensed a few years ago.

HDClear DSP includes noise reduction algorithms and filtering ambient noise of any kind to deliver “cleaner” speech to ASR (Automatic Speech Recognition). According with DSP Group website, HDClear technology outperforms other available solutions, with Word Error Rate (WER) under 20% in any ambient noise environment.

CEVA-TeakLite-III DSP core delivers the processing power providing the exceptional voice intelligibility of this DSPG HDClear chip while enabling extremely low power always-on capabilities, making HDClear is the lowest power chip of its kind in the industry, according with DSPG.

Let’s zoom on CEVA-TeakLite-III, a true 32-bit DSP addressing high-end audio processing, voice processing and wireless baseband applications. TeakLite-III is based on a fully synthesizable dual-MAC native 32-bit DSP engine forming the basis of two implementations: the CEVA-TL3210 and CEVA-TL3211 DSP cores. The CEVA-TL3210 offers a wealth of high-end features including a configurable L1 program cache memory and support for industry-standard APB and AHB-Lite system busses. The CEVA-TL3211 offers configurable L1 program and data cache memories, support for high-speed AXI system busses, and an integrated Power Scaling Unit (PSU).

Based on a native 32-bit architecture, the CEVA-TeakLite-lll can perform two 16×16-bit Multiply-Accumulate (MAC) operations or one 32×32-bit MAC in a single cycle. The CEVA-TeakLite-lll also offers:

  • Strong bit-manipulation capabilities for stream processing
  • Up to three instructions executed in parallel
  • Dedicated single-precision and double-precision FFT instructions
  • Up to 4GW program memory and 4GW data memory (16-bit words)
  • L1 program memory (cache or TCM)
  • L1 data memory (CEVA-TL3210 = TCM; CEVA-TL3211 = 2-way, set-associative, hardware-configurable cache)

An integrated Power Scaling Unit (PSU) provides advanced power management including support for clock and voltage scaling, only available with the CEVA-TL3211. This PSU is responsible for the very low-power capability of the CEVA-TeakLite-lll DSP core. This low-power feature has certainly been one of the main reasons for the DSPG HDClear design win into the Gear S2 smartwatch.

Voice recognition algorithms can require very intensive DSP computation, especially in noisy ambient environment. 20% error rate would be dramatic for any networking or storage system, but a Word Error Rate (WER) under 20% is completely acceptable for voice recognition system. If you speak to pilot your Gear S2 smartwatch using a 5 words sentence, in the worst case scenario the HDClear DSP will transmit 4 words to the main CPU. If you make a test, you realize that the recognition of 4 words in a 5 words sentence is probably enough to rebuild the initial message.

Did you know that CEVA-TeakLite family of DSPs has shipped in more than 4.5 billion devices to date, making this DSP IP core the leader in audio/voice for mobile ? Now that audio/voice is making its way into more and more devices as a means to control and activate (think of voice-controlled smart home systems, handsfree automotive systems), no doubt that CEVA-TeakLite family of DSPs are set to power billions of new devices outside in the handset space. The Samsung Gear S2 design win is the first of its kind but is truly only the beginning of a new era of smart and connected CEVA -powered devices.

Eric Esteve from IPNEST

More articles from Eric…

Share this post via:

Comments

There are no comments yet.

You must register or log in to view/post comments.