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  • Design and Optimization of Analog IP is Possible

    Designing Analog IP is often referred to as a "black art", something that only highly experienced craftsmen can produce using transistor-level techniques that aren't shared outside of their closely held group of trusted co-workers. I'd like to suggest that Analog IP can be designed and optimized by a much wider engineering audience, especially if you choose to use some automation along the way. Last year I blogged about an EDA user group meeting held in Munich, Germany and this year I attended remotely by watching an archived presentation given by Pietro Coppa of STMicroelectronics on the topic, "Design of a BandGap Voltage Reference in 40nm technology." Pietro graduated from the Universita di Catania in 2011 and works in the Catania area of Italy where they support embedded Flash (e-Flash).

    A bandgap voltage reference circuit is a temperature independent voltage reference design used inside of chips, producing a constant voltage in spite of any power supply fluctuations, temperature changes, process variation or circuit loading. Some of the analog design challenges include:

    • Yield optimization using statistical analysis
    • Mitigating effects of mismatch and process spread parameters going from 90nm to 40nm technology


    The specific EDA tool used by Pietro's group for worst case analysis, corner analysis, statistical analysis and design optimization is called WiCkeD, provided by EDA vendor MunEDA. The bandgap circuit must work across a temperature range of -40C to 150C, operate down to 0.9V, have low power consumption, and have good PSRR (Power Supply Rejection Ration) and phase margin values. Trimming is used in this circuit design to meet the yield requirements.

    For their 90nm bandgap circuit design there was about a 4% yield loss for chips operating at -40C, where the desired reference of 650mV was actually measured at 800mV. By using the Montecarlo analysis of WiCked they indeed found outlier values of 828mV for this bandgap design. An investigation of the circuit design uncovered a stable point that was different from the desired one, so they fixed the circuit and re-simulated to verify the fix. On the left is the failing circuit with two stable crossing points on IV1, and on the right side is the fixed circuit with a single stable crossing point on IV1.

    Article: How many languages an Engineer should speak?-fail-good-design-min-jpg

    On the 40nm bandgap reference circuit they needed low power consumption in standby mode, during sleep and hibernate mode the switching is off, start-up time of 15uS, and managing transitions between all operating modes properly. The voltage output of the bandgap circuit naturally spans a range of values across the temperature spectrum as shown in the chart below. Engineers simulated a DC sweep across the temperature range using 10,000 runs to determine the maximum delta in bandgap value.

    Article: How many languages an Engineer should speak?-analysis-synthesis-setup-min-jpg

    Optimization analysis was run using WiCkeD with 23 parameters for their bandgap circuit and it produced results shown in both numeric tables and a histogram chart.

    Article: How many languages an Engineer should speak?-sensitivity-yield-optimization-min-jpg

    After the first yield optimization they simulated a delta value on the bandgap of 19.6mV with a standard deviation of 2.78mV. To improve the results they made changes to a current reference then reran optimization, improving the bandgap performance by about 60% so that the delta bandgap was just 11.3mV. A buffer for VIref was also optimized using WiCkeD. The final Montecarlo analysis showed improvements in both delta bandgap and standard deviation values.

    Article: How many languages an Engineer should speak?-final-montecarlo-analysis-min-jpg

    When the 40nm first silicon came back from the foundry it showed good bandgap values for their 650mV specification across the entire temperature range, so using the optimization approach really worked out. STMicroelectronics has seen that using the WiCkeD tool during the design and optimization of 40nm analog IP blocks is helping them meet first silicon success at acceptable yield.

    To view all 21 of the MunEDA User Group Meeting presentations visit this page and complete the registration.

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