You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • How Magwel is Tapping Tried and True Business Strategy in Targeting ESD

    Often when a company starts out it takes a while for it to find the sweet spot in the marketplace. Very often it is feedback from existing customers and business success that can help point the way for small companies as they grow. This is just as true in EDA as it is in retailing or consumer products. For instance, Mentor Graphics, though not small at the time, became a significant player in the DRC market after building new technologies that customers responded to in a big way.

    Article: From SPICE Netlist back to Schematics at DAC-magwel_logo_600x386.jpg


    The EDA start up Magwel has a similar story. I first met their CEO, Dundar Dumlugol when we both worked at Cadence in the late 90's. There he was responsible for Spectre and Analog Artist, both leading products in the analog design space. It was years later that we met again after he had founded Magwel. Around 2008 we met at Starbucks in Los Gatos and he explained their then current products that were focused on TCAD for device junctions.

    At the time with my background in P&R and digital it was like listening to Greek. However, Magwel had a good technology base that allowed them to build high quality solvers for metal layers and device junctions. The customers at the time were happy with the solutions. However, for Magwel to grow significantly it needed to find additional new markets that had big growth opportunity.

    At the nudging of some of their customers they explored solving more widely applicable problems. Chief among them was ESD protection network verification and power transistor modeling. ESD protection simulation and verification is a major challenge for chip companies and much of the core solver and simulation technology Magwel had already developed was easily adapted to this application.

    Article: From SPICE Netlist back to Schematics at DAC-em-gui-cropped.jpg


    Magwel’s customers were looking for an ESD tool that would accurately predict ESD events, and identify any overcurrent and electromigration issues. The alternative tools available were too slow, overly pessimistic, were not truly simulation based or simply were too hard to use for debugging ESD issues.

    After getting numerous test cases and correctly identifying things like parasitic device triggering, electromigration violations and other problems observed in silicon, Magwel showed how well its solution works. By taking advantage of parallel processing and using TLP data to properly simulate snap back behavior, the results could be obtained quickly and matched silicon behavior extremely well. The cost of missing these issues in design can include on-tester failures, respins and even field failures.

    Article: From SPICE Netlist back to Schematics at DAC-burnout-composite.jpg


    The present capabilities of the tool continue to lead in part due to the foundation technology developed after Magwel spun out of IMEC. Working with customers on difficult test cases and their design problems, Magwel has added support for multiple device triggering and simulation for parallel current paths during an ESD event. This is different from just substituting R values for the active devices and assuming only one current path exists as is done in some other products.

    The simulator in ESDi uses the TLP IV data for each device to see if the device is actually triggered and what the final-state voltage drop and current is. The triggering of devices is based on checking whether the voltage built-up over the device during an ESD event exceeds the Vt1 voltage. The algorithm correctly models competitive triggering of parallel devices with different Vt1. This requires fully extracting and incorporating the interconnect resistance along the ESD paths as well. These are not simple point-to-point resistances, instead the tool uses multi-point resistances where the current in one current branch will affect the effective resistance seen in another.

    Set up is easy, with ESDi obtaining stack-up information from the foundry supplied ITF file and reading TLP data in a csv format. Running the tool and debugging is easy too with cross probing from the violation list to the layout with EM data overlaid in color to highlight errors.

    Magwel is working on solving the issues that affect a large number of chip companies and whose effects can frequently be tied back to yield, reliability and performance. This is a good strategy for growth. For my part I reconnected with Dundar earlier this year and have been working on several projects with them. I observed quite a change in the company direction since our previous meeting in 2008. Magwel seems well poised to continue to expand the scope of the issues they can address with their foundation technology.

    More information on Magwel's ESDi can be found here.