You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • Moving with Purpose for Certainty

    Article: From SPICE Netlist back to Schematics at DAC-columbus_voyage-jpgIn 1492 Christopher Columbus sailed from Spain towards west on Atlantic Ocean in search of Asia and Indies. Between his four voyages (1492 – 1502) he discovered many different islands and then what we call Americas. Although he had a compass with him, imagine searching a needle in a haystack. Even with localization of areas and then a smart search, still there is no guarantee of success.

    Similar is the case in the modern world with semiconductor design and manufacturing; there is a great deal of uncertainty between the chip and the design, what you get out of the fab may be far from what you design. And this uncertainty gets worse with shrinking technology nodes, new transistor structures like that of FinFETs, low noise margin and so on. The semiconductor design needs 4-6 sigma accuracy and precision for it to provide the right yield.

    So, how should semiconductor design be approached for optimum yield? To check variation, should millions of Monte Carlo (MC) simulations be run for different circuit parameters at multiple process corners? You may still miss the actual outliers. A few years ago, I had written about Solido’s Variation Designer Platform and HSMC (High Sigma Monte Carlo) method which works very fast, is accurate, and scalable over large number of process variables; it prioritizes simulations for most-likely-to-fail cases and never rejects any sample that can cause failure.

    During DAC 2015, in a panel session organized by Solido, the representatives from Cypress, Applied Micro Circuits and Microsemi presented their experiences about variation issues and their solutions. Paul McLellan already talked about Sifuei Ku’s views from Microsemi in one of his earlier blogs. I would like to delve into the views expressed by Cypress and Applied Micro as well.

    Dragomir Nikolic, CAD Director at Cypress is critical about differentiating IP where significant analog content makes a difference. He sees major portion of SoC cycle times being invested into IP. How does he improve upon cycle times applying complex set of DOEs to designs which varied amid varied experiences of designers spread across different teams in different continents? This is what he calls a change in his design methodology from “Whack-A-Mole” to “Move-With-Purpose”.

    In Dragomir’s words – “What Solido was able to do for us is, allowed us to dynamically derive the corners that truly dominate your analog design. With that, our cycle times have tremendously shrunk, our quality of results has definitely reached our internal goals for 4-sigma and we have seen tremendous improvement in the overall quality of our design” . See Dragomir’s video below

    Dragomir’s story about the most reluctant designer for change coming back after Variation Designer evaluation and asking for its license was interesting. That says - whatever you do for performance, accuracy, quality, and the like; unless your tool’s usability is good, you can’t win the designers, you fail.

    Alfred Yeung, Sr. Director of Circuits & Technologies at Applied Micro Circuits talked about different parts of a design which can be sensitive to device variation in terms of functionality and performance; and how hard it is catching the actual problems using traditional MC simulations. He presented a case study where he used high-sigma analysis using Solido Variation Designer. Solido needed to simulate only 7000 samples out of 100000 samples analyzed; and 13000 samples simulated out of 10 billion samples in another experiment with the same case. Many outliers were seen outside the design target. The issues were observed in silicon and fixed.

    In Alfred’s words – “What we’re really interested in is what happens when you run 10 billion samples. And you see here, the circuit doesn’t scale well with a lot of samples and high sigma. And there’s a design flaw here. And you see here in this particular test case it ran up to 10 billion samples, but the simulation time is only based on about 13K samples simulated so the run times were still very reasonable for us. It was something that we were not able to do in the past, and not only did we see failures we saw big outliers. The transient scale and the value scale here is not the same scale as before. But to fit everything on the same graph you will find that large number of outliers, outside the design target” . See Alfred’s video below

    During the Q/A session, all panellists were appreciative of the Variation Designer’s usability; it had no problem changing from one simulator to another, it’s very easy to use. On one particular question about technology node – the Variation Designer can be applied to any technology node. It’s more to do with variation-aware design methodology which is applicable to 130nm or higher as well as 28nm or lower nodes.

    The session also included a presentation by Jeff Dyck, VP of Technology operations at Solido. Jeff talked about his experiences with designers who have difficulties understanding variation issues, which corners to run, and crunch of time for identifying and fixing issues. Most of them end up overdesigning which was found to be the biggest issue in the survey conducted by Solido. Then he talked about the challenges in moving from old to new tools, support issues, and so on. Jeff stressed on Solido’s deeply specialized, talented, and immediate support. See Jeff’s video below for more interesting details from the survey and his experiences from his interaction with designers.

    All videos and their transcripts are here.
    Also read:
    Replacing the British Museum Algorithm
    High Yield and Performance – How to Assure?

    Pawan Kumar Fangaria
    Founder & President at